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features ? incorporates the arm7tdmi ? arm ? thumb ? processor ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt ? embedded ice in-circuit emulation, debug communication channel support internal high-speed flash ? 256 kbytes (at91sam7x256) organized in 1024 pages of 256 bytes ? 128 kbytes (at91sam7x128) orga nized in 512 pages of 256 bytes ? single cycle access at up to 30 mhz in worst case conditions ? prefetch buffer optimizing thumb instruction execution at maximum speed ? page programming time: 6 ms, including page auto-erase, full erase time: 15 ms ? 10,000 write cycles, 10-year data retention capability, sector lock capabilities, flash security bit ? fast flash programming interface for high volume production internal high-speed sram, single-cycle access at maximum speed ? 64 kbytes (at91sam7x256) ? 32 kbytes (at91sam7x128) memory controller (mc) ? embedded flash controller, abort status and misalignment detection reset controller (rstc) ? based on power-on reset cells and low-power factory-calibrated brownout detector ? provides external reset signal shaping and reset source status clock generator (ckgr) ? low-power rc oscillator, 3 to 20 mhz on-chip oscillator and one pll power management controller (pmc) ? power optimization capabilities, includin g slow clock mode (down to 500 hz) and idle mode ? four programmable external clock signals advanced interrupt controller (aic) ? individually maskable, eight-level priority, vectored interrupt sources ? two external interrupt sources and one fa st interrupt source, spurious interrupt protected debug unit (dbgu) ? 2-wire uart and support for debug communication channel interrupt, programmable ice access prevention periodic interval timer (pit) ? 20-bit programmable counter pl us 12-bit interval counter windowed watchdog (wdt) ? 12-bit key-protected programmable counter ? provides reset or interrupt signals to the system ? counter may be stopped while the processor is in debug state or in idle mode real-time timer (rtt) ? 32-bit free-running counter with alarm ? runs off the internal rc oscillator two parallel input/output controllers (pio) ? sixty-two programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt capability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output at91 arm ? thumb ? -based microcontrollers at91sam7x256/ at91sam7x128 preliminary 6120a?atarm?01-sep-05
2 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary seventeen peripheral dma controller (pdc) channels one advanced encryption system (aes) ? 128-bit key algorithm, compliant with fips pub 197 specifications ? buffer encryption/decryption capabilities with pdc one triple data encryption system (tdes) ? two-key or three-key algorithms, co mpliant with fips pub 46-3 specifications ? optimized for triple data encryption capability one usb 2.0 full speed (12 mb its per second) device port ? on-chip transceiver, 1352-byte configurable integrated fifos one ethernet mac 10/100 base-t ? media independent interface (mii) or re duced media independ ent interface (rmii) ? integrated 28-byte fifos and dedicated dma channels for transmit and receive one part 2.0a and part 2.0b compliant can controller ? eight fully-programmable message object mailboxes, 16-bit time stamp counter one synchronous serial controller (ssc) ? independent clock and frame sync sign als for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream ca pabilities with 32-bit data transfer two universal synchronous/asynchrono us receiver transmitters (usart) ? individual baud rate generator, ir da infrared modulation/demodulation ? support for iso7816 t0/t1 smart card, hardware handshaking, rs485 support ? full modem line support on usart1 two master/slave serial peripheral interfaces (spi) ? 8- to 16-bit programmable da ta length, four external peripheral chip selects one three-channel 16-bi t timer/counter (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability one four-channel 16-bit power width modulation controller (pwmc) one two-wire interface (twi) ? master mode support only, all two-wire atmel eeproms supported one 8-channel 10-bit analog-to-digital converte r, four channels multiplexed with digital i/os sam-ba ? boot assistance ? default boot program ? interface with sam-ba gr aphic user interface ieee 1149.1 jtag boundary scan on all digital pins 5v-tolerant i/os, including four high-current drive i/o lines, up to 16 ma each power supplies ? embedded 1.8v regulator, drawing up to 10 0 ma for the core and external components ? 3.3v vddio i/o lines power supply, independent 3.3v vddflash flash power supply ? 1.8v vddcore core power supply with brownout detector fully static operation: up to 55 mhz at 1.65v and 85 c worst case conditions available in a 100-lead lqfp green package
3 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 1. description atmel's at91sam7x256/128 is a member of a series of highly integrated flash microcontrollers based on the 32-bit arm risc processor. it features 256/128 kbyte high-speed flash and 64/32 kbyte sram, a large set of peripherals, including an 802.3 ethernet mac, a can control- ler, an aes 128 encryption accelera tor and a triple data encrypti on system. a co mplete set of system functions minimizes the number of external components. the embedded flash memory can be programmed in-system via the jtag-ice interface or via a parallel interface on a production programmer pr ior to mounting. built-in lock bits and a secu- rity bit protect the firmware from accidental overwrite and preserve its confidentiality. the at91sam7x256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated rc oscillator. by combining the arm7tdmi processor with on-chip flash and sram, and a wide range of peripheral functions, includin g usart, spi, can controller, et hernet mac, aes 128 accelera- tor, tdes, timer counter, rtt and analog-to-di gital converters on a monolithic chip, the at91sam7x256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring secure communication over, for example, ether- net, can wired and zigbee wireless networks. 2. configuration summary of th e at91sam7x256 and at91sam7x128 the at91sam7x256 and at91sam7x128 differ only in memory sizes. table 2-1 summarizes the configurations of the two devices. table 2-1. configuration summary device flash sram at91sam7x256 256k bytes 64k bytes at91sam7x128 128k bytes 32k bytes
4 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 3. at91sam7x256/128 block diagram figure 3-1. at91sam7x256/x128 block diagram tdi tdo tms tck nrst fiq irq0-irq1 pck0-pck3 pmc peripheral bridge peripheral dma controller aic pll rcosc sram 64/32 kbytes arm7tdmi processor ice jtag scan jtagsel pioa usart0 ssc timer counter rxd0 txd0 sck0 rts0 cts0 spi0_npcs0 spi0_npcs1 spi0_npcs2 spi0_npcs3 spi0_miso spi0_mosi spi0_spck flash 256/128 kbytes reset controller drxd dtxd tf tk td rd rk rf tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 memory controller abort status address decoder misalignment detection pio pio apb por embedded flash controller ad0 ad1 ad2 ad3 adtrg pllrc 17 channels pdc pdc usart1 rxd1 txd1 sck1 rts1 cts1 dcd1 dsr1 dtr1 ri1 pdc pdc pdc pdc spi0 pdc adc advref pdc pdc tc0 tc1 tc2 twd twck twi osc xin xout vddin pwmc pwm0 pwm1 pwm2 pwm3 1.8 v voltage regulator usb device fifo ddm ddp transceiver gnd vddout bod vddcore vddcore vddflash ad4 ad5 ad6 ad7 vddflash fast flash programming interface erase pio pgmd0-pgmd15 pgmncmd pgmen0-pgmen1 pgmrdy pgmnvalid pgmnoe pgmck pgmm0-pgmm3 vddio tst dbgu pdc pdc pit wdt rtt system controller vddcore can canrx cantx pio ethernet mac 10/100 etxck-erxck-erefck etxen-etxer ecrs-ecol, ecrsdv erxer-erxdv erx0-erx3 etx0-etx3 emdc emdio dma fifo piob spi1_npcs0 spi1_npcs1 spi1_npcs2 spi1_npcs3 spi1_miso spi1_mosi spi1_spck pdc pdc spi1 aes 128 pdc pdc ef100 sam-ba tdes pdc pdc rom vddflash
5 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 4. signal description table 4-1. signal description list signal name function type active level comments power vddin voltage regulator and adc power supply input power 3v to 3.6v vddout voltage regulator output power 1.85v vddflash flash and usb power supply power 3v to 3.6v vddio i/o lines power supply power 3v to 3.6v vddcore core power supply power 1.65v to 1.95v vddpll pll power 1.65v to 1.95v gnd ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output pllrc pll filter input pck0 - pck3 programmable clock output output ice and jtag tck test clock input no pull-up resistor tdi test data in input no pull-up resistor. tdo test data out output tms test mode select input no pull-up resistor. jtagsel jtag selection input pull-down resistor. flash memory erase flash and nvm configuration bits erase command input high pull-down resistor reset/test nrst microcontroller reset i/o low pull-up resistor, open drain output tst test mode select input high pull-down resistor debug unit drxd debug receive data input dtxd debug transmit data output aic irq0 - irq1 external interrupt inputs input fiq fast interrupt input input pio pa0 - pa30 parallel io controller a i/o pulled-up input at reset pb0 - pb30 parallel io controller b i/o pulled-up input at reset
6 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary usb device port ddm usb device port data - analog ddp usb device port data + analog usart sck0 - sck1 serial clock i/o txd0 - txd1 transmit data i/o rxd0 - rxd1 receive data input rts0 - rts1 request to send output cts0 - cts1 clear to send input dcd1 data carrier detect input dtr1 data terminal ready output dsr1 data set ready input ri1 ring indicator input synchronous serial controller td transmit data output rd receive data input tk transmit clock i/o rk receive clock i/o tf transmit frame sync i/o rf receive frame sync i/o timer/counter tclk0 - tclk2 external clock inputs input tioa0 - tioa2 i/o line a i/o tiob0 - tiob2 i/o line b i/o pwm controller pwm0 - pwm3 pwm channels output serial peripheral interface - spix spix_miso master in slave out i/o spix_mosi master out slave in i/o spix_spck spi serial clock i/o spix_npcs0 spi peripheral chip select 0 i/o low spix_npcs1-npcs3 spi peripheral chip select 1 to 3 output low two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o table 4-1. signal description list (continued) signal name function type active level comments
7 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary analog-to-digital converter ad0-ad3 analog inputs analog digital pulled-up inputs at reset ad4-ad7 analog inputs analog analog inputs adtrg adc trigger input advref adc reference analog fast flash programming interface pgmen0-pgmen1 programming enabling input pgmm0-pgmm3 programming mode input pgmd0-pgmd15 programming data i/o pgmrdy programming ready output high pgmnvalid data direction output low pgmnoe programming read input low pgmck programming clock input pgmncmd programming command input low can controller canrx can input input cantx can output output ethernet mac 10/100 erefck reference clock input rmii only etxck transmit clock input mii only erxck receive clock input mii only etxen transmit enable output etx0 - etx3 transmit data outp ut etx0 - etx1 only in rmii etxer transmit coding error output mii only erxdv receive data valid input mii only ecrsdv carrier sense and data valid input rmii only erx0 - erx3 receive data input erx0 - erx1 only in rmii erxer receive error input ecrs carrier sense input mii only ecol collision detected input mii only emdc management data clock output emdio management data input/output i/o ef100 force 100 mbits/ sec. output high rmii only table 4-1. signal description list (continued) signal name function type active level comments
8 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 5. package the at91sam7x256/128 is available in 100-lead lqfp package. 5.1 100-lead lqfp me chanical overview figure 5-1 shows the orientation of the 100-lead lqfp package. a detailed mechanical descrip- tion is given in the mechanical charac teristics section of the full datasheet. figure 5-1. 100-lead lqfp package pinout (top view) 5.2 at91sam7x25 6/128 pinout 51 76 75 50 26 25 1 100 table 5-1. pinout in 100-lead tqfp package 1 advref 26 pa18/pgmd6 51 tdi 76 tdo 2 gnd 27 pb9 52 gnd 77 jtagsel 3 ad4 28 pb8 53 pb16 78 tms 4 ad5 29 pb14 54 pb4 79 tck 5 ad6 30 pb13 55 pa23/pgmd11 80 pa30 6 ad7 31 pb6 56 pa24/pgmd12 81 pa0/pgmen0 7 vddout 32 gnd 57 nrst 82 pa1/pgmen1 8 vddin 33 vddio 58 tst 83 gnd 9 pb27/ad0 34 pb5 59 pa25/pgmd13 84 vddio 10 pb28/ad1 35 pb15 60 pa26/pgmd14 85 pa3 11 pb29/ad2 36 pb17 61 vddio 86 pa2 12 pb30/ad3 37 vddcore 62 vddcore 87 vddcore 13 pa8/pgmm0 38 pb7 63 pb18 88 pa4/pgmncmd 14 pa9/pgmm1 39 pb12 64 pb19 89 pa5/pgmrdy 15 vddcore 40 pb0 65 pb20 90 pa6/pgmnoe 16 gnd 41 pb1 66 pb21 91 pa7/pgmnvalid 17 vddio 42 pb2 67 pb22 92 erase 18 pa10/pgmm2 43 pb3 68 gnd 93 ddm 19 pa11/pgmm3 44 pb10 69 pb23 94 ddp 20 pa12/pgmd0 45 pb11 70 pb24 95 vddflash 21 pa13/pgmd1 46 pa19/pgmd7 71 pb25 96 gnd 22 pa14/pgmd2 47 pa20/pgmd8 72 pb26 97 xin/pgmck 23 pa15/pgmd3 48 vddio 73 pa27/pgmd15 98 xout 24 pa16/pgmd4 49 pa21/pgmd9 74 pa28 99 pllrc 25 pa17/pgmd5 50 pa22/pgmd10 75 pa29 100 vddpll
9 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 6. power considerations 6.1 power supplies the at91sam7x256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. the six power supply pin types are: vddin pin. it powers the voltage regulator and the adc; voltage ranges from 3.0v to 3.6v, 3.3v nominal. if the voltage regulator and the adc are not used, vddin should be connected to gnd. vddout pin. it is the output of the 1.8v voltage regulator. vddio pin. it powers the i/o lines; voltage ranges from 3.0v to 3.6v, 3.3v nominal. vddflash pin. it powers the usb transceivers and a part of the flash and is required for the flash to operate correctly; voltage ranges from 3.0v to 3.6v, 3.3v nominal. vddcore pins. they power the logic of the device; voltage ranges from 1.65v to 1.95v, 1.8v typical. it can be connected to the vddout pin with decoupling capacitor. vddcore is required for the device, including its embedded flash, to operate correctly. vddpll pin. it powers the oscillator and the pll. it can be connected directly to the vddout pin. no separate ground pins are provided for the diff erent power supplies. only gnd pins are pro- vided and should be connected as shortl y as possible to the system ground plane. 6.2 power consumption the at91sam7x256/128 has a static current of less than 60 a on vddcore at 25c, includ- ing the rc oscillator, the volt age regulator and the power-on reset when th e brownout detector is deactivated. activating the brownout detector adds 28 a static current. the dynamic power consumption on vddcore is less than 90 ma at full speed when running out of the flash. under the sa me conditions, the power consum ption on vddflash does not exceed 10 ma. 6.3 voltage regulator the at91sam7x256/128 embeds a voltage regulator that is managed by the system controller. in normal mode, the voltage regulator consumes less than 100 a static current and draws 100 ma of output current. the voltage regulator also has a low-power mode. in this mode, it consumes less than 25 a static current and draws 1 ma of output current. adequate output supply decoupling is mandator y for vddout to reduce ripple and avoid oscil- lations. the best way to achieve this is to use two capacitors in parallel: one external 470 pf (or 1 nf) npo capacitor should be connected between vddout and gnd as close to the chip as possible. one external 2.2 f (or 3.3 f) x7r capacitor should be connected between vddout and gnd. adequate input supply decouplin g is mandatory for vddin in or der to improve startup stability and reduce source voltage drop. the input decoupling capacitor should be placed close to the chip. for example, two capacitors can be used in parallel: 100 nf npo and 4.7 f x7r.
10 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 6.4 typical powe ring schematics the at91sam7x256/128 supports a 3.3v single supply mode. the internal regulator input con- nected to the 3.3v source and its output feeds vddcore and the vddpll. figure 6-1 shows the power schematics to be used for usb bus-powered systems. figure 6-1. 3.3v system single power supply schematic power source ranges from 4.5v (usb) to 18v 3.3v vddin voltage regulator vddout vddio dc/dc converter vddcore vddflash vddpll
11 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 7. i/o lines considerations 7.1 jtag port pins tms, tdi and tck are schmitt trigger inputs and are not 5-v tolerant. tms, tdi and tck do not integrate a pull-up resistor. tdo is an output, driven at up to vddio, and has no pull-up resistor. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. the jtagsel pin integrates a permanent pull-down resistor of about 15 k ? to gnd, so that it can be left unconnected for normal operations. 7.2 test pin the tst pin is used for manufacturing test or fast programming mode of the at91sam7x256/128 when asserted high. the tst pin integrates a permanent pull-down resis- tor of about 15 k ? to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, the tst pin and the pa0 and pa1 pins should be tied high and pa2 tied to low. driving the tst pin at a high level while pa0 or pa1 is driven at 0 leads to unpredictable results. 7.3 reset pin the nrst pin is bidirectional with an open drain ou tput buffer. it is handled by the on-chip reset controller and can be driven low to provide a rese t signal to the external components or asserted low externally to reset the microcontroller. there is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pu lse length. this allows connection of a sim- ple push-button on the nrst pin as system user reset, and the use of the signal nrst to reset all the components of the system. the nrst pin integrates a permanent pull-up resistor to vddio . 7.4 erase pin the erase pin is used to re-initialize the flash content and some of its nvm bits. it integrates a permanent pull-down resistor of about 15 k ? to gnd, so that it can be left unconnected for nor- mal operations. this pin is debounced by the rc oscillator to improve the glitch tolerance. minimum debouncing time is 200 ms. 7.5 pio controller lines all the i/o lines, pa0 to pa30 and pb0 to pb30, are 5v-tolerant and all integrate a programma- ble pull-up resistor. programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. 5v-tolerant means that the i/o lines can drive voltage level according to vddio, but can be driven with a voltage of up to 5.5v. however, dr iving an i/o line with a voltage over vddio while the programmable pull-up resistor is enabled can lead to unpredictable results. care should be taken, in particular at reset, as all the i/o lines default to input with pull-up resistor enabled at reset.
12 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 7.6 i/o lines current drawing the pio lines pa0 to pa3 are high-drive current capable. each of these i/o lines can drive up to 16 ma permanently. the remaining i/o lines can draw only 8 ma. however, the total current drawn by all the i/o lines cannot exceed 200 ma.
13 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 8. processor and architecture 8.1 arm7tdmi processor risc processor based on armv4t von neumann architecture ? runs at up to 55 mhz, providing 0.9 mips/mhz two instruction sets ?arm ? high-performance 32-bit instruction set ?thumb ? high code density 16-bit instruction set three-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ? execute (e) 8.2 debug and test features integrated embedded in-circuit emulator ? two watchpoint units ? test access port accessible through a jtag protocol ? debug communication channel debug unit ?two-pin uart ? debug communication channel interrupt handling ? chip id register ieee1149.1 jtag boundary-scan on all digital pins 8.3 memory controller programmable bus arbiter ? handles requests from the arm7tdmi, the ethernet mac and the peripheral dma controller address decoder provides selection signals for ? three internal 1 mbyte memory areas ? one 256 mbyte embedded peripheral area abort status registers ? source, type and all parameters of the access leading to an abort are saved ? facilitates debug by de tection of bad pointers misalignment detector ? alignment checking of all data accesses ? abort generation in case of misalignment remap command ? remaps the sram in place of the embedded non-volatile memory ? allows handling of dynamic exception vectors
14 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary embedded flash controller ? embedded flash interface, up to three programmable wait states ? prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states ? key-protected program, erase and lock/unlock sequencer ? single command for erasing, programming and locking operations ? interrupt generation in case of forbidden operation 8.4 peripheral dma controller handles data transfer between peripherals and memories seventeen channels ? two for each usart ? two for the debug unit ? two for the serial synchronous controller ? two for each serial peripheral interface ? two for the advanced encryption standard 128-bit accelerator ? two for the triple data standard encryption 128-bit acceleratorone for the analog- to-digital converter low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory next pointer management for reducing interrupt latency requirements
15 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 9. memory 9.1 at91sam7x256 256 kbytes of flash memory ? 1024 pages of 256 bytes ? fast access time, 30 mhz single-cycle access in worst case conditions ? page programming time: 6 ms, including page auto-erase ? page programming without auto-erase: 3 ms ? full chip erase time: 15 ms ? 10,000 write cycles, 10-yea r data retent ion capability ? 16 lock bits, each protecting 16 sectors of 64 pages ? protection mode to secure contents of the flash 64 kbytes of fast sram ? single-cycle access at full speed 9.2 at91sam7x128 128 kbytes of flash memory ? 512 pages of 256 bytes ? fast access time, 30 mhz single-cycle access in worst case conditions ? page programming time: 6 ms, including page auto-erase ? page programming without auto-erase: 3 ms ? full chip erase time: 15 ms ? 10,000 write cycles, 10-yea r data retent ion capability ? 8 lock bits, each protecting 8 sectors of 64 pages ? protection mode to secure contents of the flash 32 kbytes of fast sram ? single-cycle access at full speed
16 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 9.3 memory mapping 9.3.1 internal ram the at91sam7x256 embeds a high-speed 64-kbyte sram bank the at91sam7x128 embeds a high-speed 32-kbyte sram bank. after reset and until the remap command is performed, the sram is only accessible at address 0x0020 0000. after remap, the sram also becomes available at address 0x0. 9.3.2 internal rom the at91sam7x256/128 embeds an internal rom. at any time, the rom is mapped at address 0x30 0000. the rom contains ffpi and sam-ba program. 9.3.3 internal flash the at91sam7x256 features one bank of 256 kbytes of flash the at91sam7x128 features one bank of 128 kbytes of flash. at any time, the flash is mapped to address 0x0010 0000. it is also accessible at address 0x0 after the reset and before the remap command. a general purpose nvm (gpnvm) bit is used to boot either on the rom (default) or from the flash. this gpnvm bit can be cleared or set respecti vely through the commands ?clear general-pur- pose nvm bit? and ?set general-purpose nvm bit? of the efc user interface. setting the gpnvm bit 2 selects the boot from the flash. asserting erase clears the gpnvm bit 2 and thus selects the boot from the rom by default. figure 9-1. internal memory mapping with gpnvm bit 2 = 0 (default) 256m bytes rom before remap sram after remap undefined areas (abort) 0x000f ffff 0x001f ffff 0x002f ffff 0x0fff ffff 1 m bytes 1 m bytes 1 m bytes 252 m bytes internal flash internal sram 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 internal rom 0x003f ffff 0x0040 0000 1 m bytes
17 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 9-2. internal memory mapping with gpnvm bit 2 = 1 9.4 embedded flash 9.4.1 flash overview the flash of the at91sam7x256 is organized in 1024 pages of 256 bytes. it reads as 65,536 32-bit words. the flash of the at91sam7x128 is organized in 512 pages of 256 bytes. it reads as 32,768 32-bit words. the flash contains a 256-byte write buffer, accessible through a 32-bit interface. the flash benefits from the integration of a power reset cell and from the brownout detector. this prevents code corruption during power su pply changes, even in the worst conditions. when flash is not used (read or write access), it is automatically placed into standby mode. 9.4.2 embedded flash controller the embedded flash controller (efc) manages accesses performed by the masters of the sys- tem. it enables reading the flash and writing the write buffer. it also contains a user interface, mapped within the memory co ntroller on the apb. the user interface allows: programming of the access parameters of the flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, nvm bit set, nvm bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors the embedded flash controller also provides a dual 32-bit prefetch buffer that optimizes 16-bit access to the flash. this is particularly efficient when the processor is running in thumb mode. 256m bytes flash before remap sram after remap undefined areas (abort) 0x000f ffff 0x001f ffff 0x002f ffff 0x0fff ffff 1 m bytes 1 m bytes 1 m bytes 252 m bytes internal flash internal sram 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 internal rom 0x003f ffff 0x0040 0000 1 m bytes
18 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 9.4.3 lock regions 9.4.3.1 at91sam7x256 the embedded flash controller manages 16 lock bi ts to protect 16 regions of the flash against inadvertent flash erasing or programming co mmands. the at91sam7x256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. each lock region has a size of 16 kbytes. if a locked-region?s erase or program command occurs, the command is aborted and the efc trigs an interrupt. the 16 nvm bits are software programmable through the efc user interface. the command ?set lock bit? enables the pr otection. the command ?clear lo ck bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 9.4.3.2 at91sam7x128 the embedded flash controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. the at91sam7x128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. each lock region has a size of 16 kbytes. if a locked-region?s erase or program command occurs, the command is aborted and the efc trigs an interrupt. the 8 nvm bits are software programmable through the efc user interface. the command ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 9.4.4 security bit feature the at91sam7x256/128 features a security bit, based on a specific nvm-bit. when the secu- rity is enabled, any access to the flash, either through the ice interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code pro- grammed in the flash. this security bit can only be enabled, through the command ?set security bit? of the efc user interface. disabling the security bit can only be achieved by asse rting the erase pin at 1, and after a full flash erase is performed. when the se curity bit is deactivated, all accesses to the flash are permitted. it is important to note that the assertion of the erase pin should always be longer than 200 ms. as the erase pin integrates a permanent pull-down, it can be left unconnected during normal operation. however, it is safer to connect it directly to gnd fo r the final application. 9.4.5 non-volatile brownout detector control two general purpos e nvm (gpnvm) bits are used for c ontrolling the brownout detector (bod), so that even after a power loss, the brownout detector operations remain in their state. these two gpnvm bits can be cleared or set respectively through the commands ?clear gen- eral-purpose nvm bit? and ?set general-pu rpose nvm bit? of the efc user interface.
19 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary gpnvm bit 0 is used as a brownout detector enable bit. setting the gpnvm bit 0 enables the bod, clearing it disables the bod. asserting erase clears the gpnvm bit 0 and thus disables the brownout detector by default. the gpnvm bit 1 is used as a brownout reset enable signal for the reset controller. setting the gpnvm bit 1 enables the brownout reset when a brownout is detected, clearing the gpnvm bit 1 disables the brownout reset. asserting erase disables the brownout reset by default. 9.4.6 calibration bits eight nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user. the erase pin has no effect on the calibration bits. 9.5 fast flash programming interface the fast flash programming interface allows programming the device through either a serial jtag interface or through a multiplexed fully-han dshaked parallel port. it allows gang-program- ming with market-standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when the tst pin and the pa0 and pa1 pins are all tied high and pa2 tied to low. 9.6 sam-ba boot assistant the sam-ba boot assistant is a default boot program that provides an easy way to program in- situ the on-chip flash memory. the sam-ba boot assistant supports serial co mmunication via the dbgu or the usb device port. communication via the dbgu supports a wide range of crystals from 3 to 20 mhz via software auto-detection. communication via the usb device port is limited to an 18.432 mhz crystal. the sam-ba boot provides an interface with sam-ba graphic user interface (gui). the sam-ba boot is in rom and is mapped in fl ash at address 0x0 when the gpnvm bit 2 is set to 0.
20 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 10. system controller the system controller manages a ll vital blocks of the microcontr oller: interrupts , clocks, power, time, debug and reset. figure 10-1. system controller block diagram nrst slck advanced interrupt controller real-time timer periodic interval timer reset controller pa0-pa30 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controller por bod rcosc gpnvm[0] cal en power management controller osc pll xin xout pllrc mainck pllck pit_irq mck proc_nreset wdt_irq periph_irq{2-3] periph_nreset periph_clk[2..18] pck mck pmc_irq udpck nirq nfiq rtt_irq embedded peripherals periph_clk[2-3] pck[0-3] in out enable arm7tdmi slck slck irq0-irq1 fiq irq0-irq1 fiq periph_irq[4..19] periph_irq[2..19] int int periph_nreset periph_clk[4..19] embedded flash flash_poe jtag_nreset flash_poe gpnvm[0..2] flash_wrdis flash_wrdis proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq efc_irq slck gpnvm[1] boundary scan tap controller jtag_nreset ice_nreset debug pck debug idle debug memory controller mck proc_nreset bod_rst_en proc_nreset periph_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset force_ntrst dbgu_txd usb device port udpck periph_nreset periph_clk[11] periph_irq[11] usb_suspend usb_suspend voltage regulator standby voltage regulator mode controller security_bit cal ice_nreset force_ntrst cal pb0-pb30 efc_irq
21 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 10.1 system controller mapping the system controller peripherals are all mapped to the highest 4 kbytes of address space, between addresses 0xffff f000 and 0xffff ffff. figure 10-2 shows the mapping of the system controller. note that the memory controller con- figuration user interface is also mapped within this address space. figure 10-2. system controller mapping 0xffff f000 0xffff f200 0xffff f1ff 0xffff f3ff 0xffff f5ff 0xffff fbff 0xffff fcff 0xffff feff 0xffff ffff 0xffff f400 0xffff f800 0xffff fc00 0xffff fd0f 0xffff fc2f 0xffff fc3f 0xffff fd4f 0xffff fc6f 0xffff f600 0xffff f7ff aic dbgu pioa reserved pmc mc advanced interrupt controller debug unit pio controller a power management controller memory controller 0xffff fd00 0xffff ff00 rstc pit rtt wdt vreg reserved reserved reserved 0xffff fd20 0xffff fd30 0xffff fd40 0xffff fd60 0xffff fd70 reset controller real-time timer periodic interval timer watchdog timer voltage regulator mode controller 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers 256 bytes/64 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 256 bytes/64 registers 4 bytes/1 register piob pio controller b 512 bytes/128 registers peripheral name size address peripheral
22 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 10.2 reset controller based on one power-on reset cell and one brownout detector status of the last reset, either power-up reset, software reset, user reset, watchdog reset, brownout reset controls the internal resets and the nrst pin output allows to shape a signal on the nrst line, guaranteeing that the length of the pulse meets any requirement. 10.2.1 brownout detector and power-on reset the at91sam7x256/x128 embeds one brownout detec tion circuit and a power-on reset cell. the power-on reset is supplie d with and monitors vddcore. both signals are provided to the flash to prev ent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. the power-on reset cell has a limited-accuracy threshold at around 1.5v. its output remains low during power-up until vddcore go es over this voltag e level. this signal goes to the reset con- troller and allows a full re-initialization of the device. the brownout detector monitors the vddcor e and vddflash levels during operation by comparing them to a fixed trigger level. it secures system operations in the most difficult environ- ments and prevents code corruption in case of brownout on the vddcore or vddflash. when the brownout detector is enabled and vddcor e decreases to a value below the trigger level (vbot18-, defined as vbot18 - hyst/2), the brownout output is immediately activated. when vddcore increases above the trigger leve l (vbot18+, defined as v bot18 + hyst/2), the reset is released. the brownout detector only detects a drop if the voltage on vddcore stays below the threshold voltage for longer than about 1s. the vddcore threshold voltage ha s a hysteresis of about 50 mv , to ensure spike free brown- out detection. the typical value of the brownout detector threshold is 1.68v with an accuracy of 2% and is factory calibrated. when the brownout detector is enabled and vddflash decreases to a value below the trigger level (vbot33-, defined as vbot33 - hyst/2), the brownout output is immediately activated. when vddflash increases above the trigger level (vbot33+, defined as vbot33 + hyst/2), the reset is released. the brownout detector only detects a drop if the voltage on vddcore stays below the threshold voltage for longer than about 1s. the vddflash threshold voltage has a hysteresis of about 50 mv, to ensure spike free brown- out detection. the typical value of the brownout detector threshold is 2.80v with an accuracy of 3.5% and is factory calibrated. the brownout detector is low-power, as it consum es less than 28 a static current. however, it can be deactivated to save its static current. in this case, it consumes less than 1a. the deac- tivation is configured through the gpnvm bit 0 of the flash.
23 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 10.3 clock generator the clock generator embeds one low-power rc oscillator, one main oscillator and one pll with the following characteristics: rc oscillator ranges betw een 22 khz and 42 khz main oscillator frequency ranges between 3 and 20 mhz main oscillator can be bypassed pll output ranges between 80 and 220 mhz it provides slck, mainck and pllck. figure 10-3. clock generator block diagram embedded rc oscillator main oscillator pll and divider clock generator power management controller xin xout pllrc slow clock slck main clock mainck pll clock pllck control status
24 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 10.4 power management controller the power management controller uses the clock generator outputs to provide: the processor clock pck the master clock mck the usb clock udpck all the peripheral clocks, independently controllable four programmable clock outputs the master clock (mck) is programmable from a few hundred hz to the maximum operating fre- quency of the device. the processor clock (pck) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. figure 10-4. power management co ntroller block diagram 10.5 advanced interrupt controller controls the interrupt lines (nirq and nfiq) of an arm processor individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (rtt, pit, efc, pmc, dbgu, etc.) ? other sources control the peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive external sources 8-level priority controller ? drives the normal interrupt nirq of the processor ? handles priority of the interrupt sources mck periph_clk[2..18] int udpck slck mainck pllck prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller peripherals clock controller on/off usb clock controller on/off slck mainck pllck prescaler /1,/2,/4,...,/64 programmable clock controller pllck divider /1,/2,/4 pck[0..3]
25 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary ? higher priority interrupts can be served during service of lower priority interrupt vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations fast forcing ? permits redirecting any interrupt source on the fast interrupt general interrupt mask ? provides processor synchronization on events without triggering an interrupt 10.6 debug unit comprises: ? one two-pin uart ? one interface for the debug co mmunication channel (dcc) support ? one set of chip id registers ? one interface providing ice access prevention two-pin uart ? usart-compatible user interface ? programmable baud rate generator ? parity, framing and overrun error ? automatic echo, local loopback and remote loopback channel modes debug communication channel support ? offers visibility of commrx and comm tx signals from the arm processor chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals ? chip id is 0x271b 0940 (version 0) for at91sam7x256 ? chip id is 0x271a 0740 (version 0) for at91sam7x128 10.7 period interval timer 20-bit programmable counter plus 12-bit interval counter 10.8 watchdog timer 12-bit key-protected programmable counter running on prescaled slck provides reset or interrupt signals to the system counter may be stopped while the processor is in debug state or in idle mode 10.9 real-time timer 32-bit free-running counter with alarm running on prescaled slck programmable 16-bit prescaler for slck accuracy compensation
26 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 10.10 pio controllers two pio controllers, each controlling 31 i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general-purpose i/o) ? input change interrupt ? half a clock period glitch filter ? multi-drive option enables driving in open drain ? programmable pull-up on each i/o line ? pin data status register, supplies visib ility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write 10.11 voltage regulator controller the purpose of this controller is to select the power mode of the voltage regulator between normal mode (bit 0 is cleared) or standby mode (bit 0 is set).
27 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 11. peripherals 11.1 peripheral mapping each peripheral is allocated 16 kbytes of address space. figure 11-1. user peripheral mapping peripheral name size 16 kbytes 0xfffa 0000 0xfffa 3fff tc0, tc1, tc2 timer/counter 0, 1 and 2 16 kbyte s 16 kbyte s 16 kbytes reserved 0xfffa 7fff 0xf000 0000 twi two-wire interface 0xfffb 8000 usart0 universal synchronous asynchronous receiver transmitter 0 0xfffc 0000 0xfffc 3fff usart1 universal synchronous asynchronous receiver transmitter 1 0xfffc 4000 0xfffc 7fff ssc serial synchronous controller 0xfffd 4000 0xfffd 7fff 0xfffd 3fff 0xfffd ffff spi0 serial peripheral interface 0 0xfffe 0000 0xfffe 7fff reserved 0xfffe ffff 0xfffe 8000 0xfffb 4000 0xfffb 7fff reserved 0xfff9 ffff 16 kbytes 0xfffc ffff 0xfffd 8000 0xfffd bfff adc analog-to-digital converter 16 kbyte s 0xfffc bfff 0xfffc c000 0xfffb ffff reserved 0xfffb c000 0xfffb bfff pwmc 16 kbytes 0xfffa bfff 0xfffb 0000 0xfffb 3fff udp usb device port 16 kbytes 0xfffd 0000 0xfffd c000 can emac ethernet mac 16 kbyte s 0xfffe 3fff spi1 serial peripheral interface 1 0xfffe 4000 16 kbyte s 0xfffc 8000 16 kbytes advanced encryption standard 128-bit aes 128 tdes reserved triple data encryption standard 0xfffa 8000 0xfffa 4000 16 kbyte s 16 kbyte s reserved 0xfffa c000 0xfffa ffff pwm controller 16 kbytes can controller
28 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 11.2 peripheral multiplexing on pio lines the at91sam7x256/128 features two pio controlle rs, pioa and piob, that multiplex the i/o lines of the peripheral set. each pio controller controls 31 lines. each line can be assigned to one of two peripheral func- tions, a or b. some of them can also be mu ltiplexed with the anal og inputs of the adc controller. table 11-1 on page 29 and table 11-2 on page 30 defines how the i/o lines of the peripherals a, b or the analog inputs are multiplexed on the pio controller a and pio controller b. the two columns ?function? and ?comments? have been inserted for the user?s own comments; they may be used to track how pins are defined in an application. note that some peripheral functions that are output only, may be duplicated in the table. at reset, all i/o lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.
29 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 11.3 pio controller a multiplexing table 11-1. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b comments function comments pa0 rxd0 high-drive pa1 txd0 high-drive pa2 sck0 spi1_npcs1 high-drive pa3 rts0 spi1_npcs2 high-drive pa4 cts0 spi1_npcs3 pa 5 r x d 1 pa 6 t x d 1 pa7 sck1 spi0_npcs1 pa8 rts1 spi0_npcs2 pa9 cts1 spi0_npcs3 pa 1 0 t w d pa 1 1 t w c k pa12 spi_npcs0 pa13 spi0_npcs1 pck1 pa14 spi0_npcs2 irq1 pa15 spi0_npcs3 tclk2 pa16 spi0_miso pa17 spi0_mosi pa18 spi0_spck pa19 canrx pa20 cantx pa21 tf spi1_npcs0 pa22 tk spi1_spck pa23 td spi1_mosi pa24 rd spi1_miso pa25 rk spi1_npcs1 pa26 rf spi1_npcs2 pa27 drxd pck3 pa 2 8 d t x d pa29 fiq spi1_npcs3 pa 3 0 irq0 pck2
30 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 11.4 pio controller b multiplexing table 11-2. multiplexing on pio controller b pio controller a application usage i/o line peripheral a peripheral b comments function comments pb0 etxck/erefck pck0 pb1 etxen pb2 etx0 pb3 etx1 pb4 ecrs pb5 erx0 pb6 erx1 pb7 erxer pb8 emdc pb9 emdio pb10 etx2 spi1_npcs1 pb11 etx3 spi1_npcs2 pb12 etxer tclk0 pb13 erx2 spi0_npcs1 pb14 erx3 spi0_npcs2 pb15 erxdv/ecrsdv pb16 ecol spi1_npcs3 pb17 erxck spi0_npcs3 pb18 ef100 adtrg pb19 pwm0 tclk1 pb20 pwm1 pck0 pb21 pwm2 pck1 pb22 pwm3 pck2 pb23 tioa0 dcd1 pb24 tiob0 dsr1 pb25 tioa1 dtr1 pb26 tiob1 ri1 pb27 tioa2 pwm0 ad0 pb28 tiob2 pwm1 ad1 pb29 pck1 pwm2 ad2 pb30 pck2 pwm3 ad3
31 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 11.5 peripheral identifiers the at91sam7x256/128 embeds a wide range of peripherals. table 11-3 defines the periph- eral identifiers of the at91sam7x256/128. unique peripheral identifiers are defined for both the advanced interrupt controller and the power management controller. note: 1. setting sysirq and adc bits in the clock set/clear registers of the pmc has no effect. the system controller and adc are continuously clocked. table 11-3. peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1 sysirq (1) 2 pioa parallel i/o controller a 3 piob parallel i/o controller b 4 spi0 serial peripheral interface 0 5 spi1 serial peripheral interface 1 6 us0 usart 0 7 us1 usart 1 8 ssc synchronous serial controller 9 twi two-wire interface 10 pwmc pulse width modulation controller 11 udp usb device port 12 tc0 timer/counter 0 13 tc1 timer/counter 1 14 tc2 timer/counter 2 15 can can controller 16 emac ethernet mac 17 adc (1) analog-to digital converter 18 aes advanced encryption standard 128-bit 19 tdes triple data encryption standard 20-29 reserved 30 aic advanced interrupt controller irq0 31 aic advanced interrupt controller irq1
32 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 11.6 ethernet mac dma master on receive and transmit channels compatible with ieee standard 802.3 10 and 100 mbit/s operation full- and half-duplex operation statistics counter registers mii/rmii interface to the physical layer interrupt generation to signal receive and transmit completion 28-byte transmit fifo and 28-byte receive fifo automatic pad and crc generation on transmitted frames automatic discard of frames received with errors address checking logic supports up to four specific 48-bit addresses support promiscuous mode where all valid received frames are copied to memory hash matching of unicast an d multicast destination addresses physical layer management through mdio interface half-duplex flow control by forc ing collisions on incoming frames full-duplex flow control with recognition of incoming pause frames support for 802.1q vlan tagging with recognition of incoming vlan and priority tagged frames multiple buffers per receive and transmit frame jumbo frames up to 10240 bytes supported 11.7 serial peripheral interface supports communication with external serial devices ? four chip selects with external decoder allow communication with up to 15 peripherals ? serial memories, such as dataflash ? and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays per chip select, between consecutive transfers and between clock and data ? programmable delay between consecutive transfers ? selectable mode fault detection ? maximum frequency at up to master clock 11.8 two-wire interface master mode only compatibility with standard two-wire serial memories
33 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary one, two or three bytes for slave address sequential read/write operations 11.9 usart programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode ? 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb or lsb first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? hardware handshaking rts - cts ? modem signals management dtr-dsr-dcd-ri on usart1 ? receiver time-out and transmitter timeguard ? multi-drop mode with address generation and detection rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo 11.10 serial synchronous controller provides serial synchronous communication links used in audio and telecom applications contains an independent receiver and transmitter and a common clock divider offers a configurable frame sync and data length receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal receiver and transmitter include a data signal , a clock signal and a frame synchronization signal 11.11 timer counter three 16-bit timer counter channels ? three output compare or two input capture wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation
34 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary ? delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs five internal clock inputs, as defined in table 11-4 ? two multi-purpose input/output signals ? two global registers that act on all three tc channels 11.12 pulse width modulation controller four channels, one 16-bit counter per channel common clock generator, providing thirteen different clocks ? one modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs independent channel programming ? independent enable/disable commands ? independent clock selection ? independent period and duty cycle, with double buffering ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform 11.13 usb device port usb v2.0 full-speed compliant,12 mbits per second embedded usb v2.0 full-speed transceiver embedded 1352-byte dual-port ram for endpoints six endpoints ? endpoint 0: 8 bytes ? endpoint 1 and 2: 64 bytes ping-pong ? endpoint 3: 64 bytes ? endpoint 4 and 5: 256 bytes ping-pong ? ping-pong mode (two memory banks) for bulk endpoints suspend/resume logic table 11-4. timer counter clocks assignment tc clock input clock timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 mck/1024
35 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 11.14 can controller fully compliant with can 2.0a and 2.0b bit rates up to 1mbit/s eight object oriented mailboxes each with the following properties: ? can specification 2.0 part a or 2.0 part b programmable for each message ? object configurable to receive (with overwrite or not) or transmit ? local tag and mask filters up to 29-bit identifier/channel ? 32-bit access to data register s for each mailbox data object ? uses a 16-bit time stamp on receive and transmit message ? hardware concatenation of id unmasked bitfields to speedup family id processing ? 16-bit internal timer for time stamping and network synchronization ? programmable reception buffer length up to 8 mailbox objects ? priority management between transmission mailboxes ? autobaud and listening mode ? low power mode and programmable wake-up on bus activity or by the application ? data, remote, error and overload frame handling 11.15 128-bit advanced e ncryption standard compliant with fips publication 197, advanced encryption standard (aes) 128-bit cryptographic key 12-clock cycles encryption/decryption processing time support of the five standard modes of operation specified in the nist special publication 800-38a: ? electronic codebook (ecb) ? cipher block chaining (cbc) ? cipher feedback (cfb) ? output feedback (ofb) ? counter (ctr) 8-, 16-, 32-, 64- and 128-bit data sizes possible in cfb mode last output data mode allowing message authentication code (mac) generation hardware countermeasures against differential power analysis attacks connection to pdc channel capa bilities optimizes data transf ers for all operating modes: ? one channel for the receiver, one channel for the transmitter ? next buffer support aes 128-bit ke y algorithm hardwa re accelerator 11.16 triple data encryption standard single data encryption standard (des) and triple data encryption algorithm (tdea or tdes) supports compliant with fips publication 46-3 , data encryption standard (des) 64-bit cryptographic key two-key or three-key algorithms
36 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 18-clock cycles encryption/decryption processing time for des 50-clock cycles encryption/decryption processing time for tdes support the four standard modes of operation specified in the fips publication 81, des modes of operation: ? electronic codebook (ecb) ? cipher block chaining (cbc) ? cipher feedback (cfb) ? output feedback (ofb) 8-, 16-, 32- and 64- data sizes possible in cfb mode last output data mode allowing optimized message (data) authentication code (mac) generation connection to pdc channel capa bilities optimizes data transf ers for all operating modes: ? one channel for the receiver, one channel for the transmitter ? next buffer support 11.17 analog-to-digital converter 8-channel adc 10-bit 384 ksamples/sec. successi ve approximation register adc -3/+3 lsb integral non linearity, -2/+2 lsb differential non linearity integrated 8-to-1 multiplexer, offering eight independent 3.3v analog inputs external voltage reference for better accuracy on low voltage inputs individual enable and disable of each channel multiple trigger sources ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels four of eight analog inputs shared with digital signals
37 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 12. arm7tdmi proc essor overview 12.1 overview the arm7tdmi core executes both the 32-bit arm ? and 16-bit thumb ? instruction sets, allow- ing the user to trade off between high per formance and high code density.the arm7tdmi processor implements von neuman architecture, using a three-stage pipeline consisting of fetch, decode, and execute stages. the main features of the arm7tdmi processor are: arm7tdmi based on armv4t architecture two instruction sets ?arm ? high-performance 32-bit instruction set ?thumb ? high code density 16-bit instruction set three-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ? execute (e)
38 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 12.2 arm7tdmi processor for further details on arm7tdmi, refer to the following arm documents: arm architecture reference manual (ddi 0100e) arm7tdmi technical reference manual (ddi 0210b) 12.2.1 instruction type instructions are either 32 bits long (in arm state) or 16 bits long (in thumb state). 12.2.2 data type arm7tdmi supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. words must be aligned to four-byte boundaries and half words to two-byte boundaries. unaligned data access behavior depends on which instruction is used where. 12.2.3 arm7tdmi operating mode the arm7tdmi, based on arm architecture v4t, supports seven processor modes: user : the normal arm program execution state fiq : designed to support high-speed data transfer or channel process irq : used for general-purpose interrupt handling supervisor : protected mode for the operating system abort mode : implements virtual memory and/or memory protection system : a privileged user mode for the operating system undefined : supports software emulation of hardware coprocessors mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. most application programs execute in user mode. the non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protecte d resources. 12.2.4 arm7tdmi registers the arm7tdmi processor has a total of 37registers: 31 general-purpose 32-bit registers 6 status registers these registers are not accessible at the same time. the processor state and operating mode determine which registers are available to the programmer. at any one time 16 registers are visible to the user. the remainder are synonyms used to speed up exception processing. register 15 is the program counter (pc) and c an be used in all instructions to reference data relative to the current instruction. r14 holds the return address after a subroutine call. r13 is used (by software convention) as a stack pointer.
39 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary registers r0 to r7 are unbanked registers. this means that each of them refers to the same 32- bit physical register in all processor modes. they are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a general- purpose register to be specified. registers r8 to r14 are banked registers. this means that each of them depends on the current mode of the processor. 12.2.4.1 modes and exception handling all exceptions have banked registers for r14 and r13. after an exception, r14 holds the return address for exception processing. this address is used to return after the exception is processed, as well as to address the instruction that caused the exception. r13 is banked across exception modes to provide each exception handler with a private stack pointer. the fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin with- out having to save these registers. table 12-1. arm7tdmi arm modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr spsr_svc spsr_abort spsr_undef spsr_irq spsr_fiq mode-specific banked registers
40 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary a seventh processing mode, system mode, does not have any banked registers. it uses the user mode registers. system mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 12.2.4.2 status registers all other processor states are held in status registers. the current operating processor status is in the current program status register (cpsr). the cpsr holds: four alu flags (negative, zero, carry, and overflow) two interrupt disable bits (one for each type of interrupt) one bit to indicate arm or thumb execution five bits to encode the current processor mode all five exception modes also have a saved program status register (spsr) that holds the cpsr of the task immediately preceding the exception. 12.2.4.3 exception types the arm7tdmi supports five types of exception and a privileged processing mode for each type. the types of exceptions are: fast interrupt (fiq) normal interrupt (irq) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (swis) exceptions are generated by internal and external sources. more than one exception can occur in the same time. when an exception occurs, the banked version of r14 and the spsr for the exception mode are used to save state. to return after handling the exception, the spsr is moved to the cpsr, and r14 is moved to the pc. this can be done in two ways: by using a data-processing instruction with the s-bit set, and the pc as the destination by using the load multiple with restore cpsr instruction (ldm) 12.2.5 arm instruction set overview the arm instruction set is divided into: branch instructions data processing instructions status register transfer instructions load and store instructions coprocessor instructions exception-generating instructions arm instructions can be executed conditionally. every instruction contains a 4-bit condition code field (bit[31:28]). table 12-2 gives the arm instruction mnemonic list.
41 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 12.2.6 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: branch instructions data processing instructions load and store instructions load and store multiple instructions exception-generating instruction in thumb mode, eight general-purpose registers, r0 to r7, are available that are the same physical registers as r0 to r7 when executing arm instructions. some thumb instructions also access to the program counter (arm register 15), the link register (arm register 14) and the table 12-2. arm instruction mnemonic list mnemonic operation mnemonic operation mov move cdp coprocessor data processing add add mvn move not sub subtract adc add with carry rsb reverse subtract sbc subtract with carry cmp compare rsc reverse subtract with carry tst test cmn compare negated and logical and teq test equivalence eor logical exclusiv e or bic bit clear mul multiply orr logical (inclusive) or smull sign long multiply mla multiply accumulate smlal signed long multiply accumulate umull unsigned long multiply msr move to status register umla l unsigned long multiply accumulate b branch mrs move from status register bx branch and exchange bl branch and link ldr load word swi software interrupt ldrsh load signed halfword str store word ldrsb load signed byte strh store half word ldrh load half word strb store byte ldrb load byte strbt store register byte with translation ldrbt load register byte with translati on strt store register with translation ldrt load register with translation stm store multiple ldm load multiple swpb swap byte swp swap word mrc move from coprocessor mcr move to coprocessor stc store from coprocessor ldc load to coprocessor
42 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary stack pointer (arm register 13). further instru ctions allow limited access to the arm registers 8 to 15. table 12-3 gives the thumb instruction mnemonic list. table 12-3. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack
43 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 13. debug and test features 13.1 description the at91sam7x series features a number of complementar y debug and test capabilities. a common jtag/ice (in-circuit emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. the debug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt handling of the internal commtx and commrx signals that trace the activity of the debug communication channel. a set of dedicated deb ug and test input/out put pins gives direct access to these capabilities from a pc-based test environment. 13.2 block diagram figure 13-1. debug and test block diagram ice pdc dbgu pio drxd dtxd tst tms tck tdi jtagsel tdo boundary ta p ice/jtag ta p arm7tdmi reset and test por
44 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 13.3 application examples 13.3.1 debug environment figure 13-2 shows a complete debug environment example. the ice/jtag interface is used for standard debugging functions, such as downloading code and single-stepping through the program. figure 13-2. application debug environment example at91sam7xxx-based application board ice/jtag interface host debugger ice/jtag connector at91sam7xxx terminal rs232 connector
45 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 13.3.2 test environment figure 13-3 shows a test environment example. test vectors are sent and interpreted by the tester. in this example, the ?board in test? is designed using a number of jtag-compliant devices. these devices can be connected to form a single scan chain. figure 13-3. application test environment example 13.4 debug and test pin description tester jtag interface ice/jtag connector at91sam7xxx-based application board in test at91sam7xxx test adaptor chip 2 chip n chip 1 table 13-1. debug and test pin list pin name function type active level reset/test nrst microcontroller reset input/output low tst test mode select input high ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input jtagsel jtag selection input debug unit drxd debug receive data input dtxd debug transmit data output
46 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 13.5 functional description 13.5.1 test pin one dedicated pin, tst, is used to define the device operating mode. the user must make sure that this pin is tied at low level to ensure normal operating conditions. other values associated with this pin are reserved for manufacturing test. 13.5.2 embedded in-circuit emulator the arm7tdmi embedded in-circuit emulator is supported via the ice/jtag port.the internal state of the arm7tdmi is examined through an ice/jtag port. the arm7tdmi processor contains hardware ex tensions for advanced debugging features: in halt mode, a store-multiple (stm) can be inserted into the instruction pipeline. this exports the contents of the arm7tdmi registers. this data can be serially shifted out without affecting the rest of the system. in monitor mode, the jtag interface is used to transfer data between the debugger and a simple monitor program running on the arm7tdmi processor. there are three scan chains inside the arm7tdmi processor that support testing, debugging, and programming of the embedded ice. the scan chains are controlled by the ice/jtag port. embedded ice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed after jtagsel is changed. for further details on the embedded in-circuit-emu lator, see the arm7tdmi (rev4) technical reference manual (ddi0210b). 13.5.3 debug unit the debug unit provides a two-pin (dxrd a nd txrd) usart that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and that trace the activity of the debug communication channel. the debug unit allows blockage of access to the system through the ice interface. a specific register, the debug unit chip id register, gives information about the product version and its internal configuration. the at91sam7x256 debug unit chip id value is 0x271b 0940 on 32-bit width. the at91sam7x128 debug unit chip id value is 0x271a 0740 on 32-bit width. for further details on the debug unit, see the debug unit section. 13.5.4 ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packaging technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, extest and bypass functions are implemented. in ic e debug mode, the arm proce ssor responds
47 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary with a non-jtag ch ip id that identifi es the processo r to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be per- formed after jtagsel is changed. a boundary-scan descriptor language (bsdl) file is provided to set up test. 13.5.4.1 jtag boundary-scan register the boundary-scan register (bsr) contains 187 bits that correspond to active pins and associ- ated control signals. each at91sam7x input/output pin corresponds to a 3-bit register in the bsr. the output bit contains data that can be forced on the pad. the input bit facilitates the observability of data applied to the pad. the control bit selects the direction of the pad. table 13-2. at91sam7x jtag boundary scan register bit number pin name pin type associated bsr cells 187 pa30/irq0/pck2 in/out input 186 output 185 control 184 pa0/rxd0 in/out input 183 output 182 control 181 pa1/txd0 in/out input 180 output 179 control 178 pa3/rts0/spi1_npcs2 in/out input 177 output 176 control 175 pa2/sck0/spi1_npcs1 in/out input 174 output 173 control 172 pa4/cts0/spi1_npcs3 in/out input 171 output 170 control 169 pa5/rxd1 in/out input 168 output 167 control 166 pa6/txd1 in/out control 165 input 164 output
48 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 163 pa7/sck1/spi0_npcs1 in/out control 162 input 161 output 160 erase in input 159 pb27/tioa2/pwm0/ad0 in/out input 158 output 157 control 156 pb28/tiob2/pwm1/ad1 in/out input 155 output 154 control 153 pb29/pck1/pwm2/ad2 in/out input 152 output 151 control 150 pb30/pck2/pwm3/ad3 in/out input 149 output 148 control 147 pa8/rts1/spi0_npcs2 in/out input 146 output 145 control 144 pa9/cts1/spi0_npcs3 in/out input 143 output 142 control 141 pa10/twd in/out input 140 output 139 control 138 pa11/twck in/out input 137 output 136 control 135 pa12/spi0_npcs0 in/out input 134 output 133 control 132 pa13/spi0_npcs1/pck1 in/out input 131 output 130 control table 13-2. at91sam7x jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
49 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 129 pa14/spi0_npcs2/irq1 in/out input 128 output 127 control 126 pa15/spi0_npcs3/tclk2 in/out input 125 output 124 control 123 pa16/spi0_miso in/out input 122 output 121 control 120 pa17/spi0_mosi in/out input 119 output 118 control 117 pa18/spi0_spck in/out input 116 output 115 control 114 pb9/emdio in/out input 113 output 112 control 111 pb8/emdc in/out input 110 output 109 control 108 pb14/erx3/spi0_npcs2 in/out input 107 output 106 control 105 pb13/erx2/spi0_npcs1 in/out input 104 output 103 control 102 pb6/erx1 in/out input 101 output 100 control 99 pb5/erx0 in/out input 98 output 97 control table 13-2. at91sam7x jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
50 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 96 pb15/erxdv/ecrsdv in/out input 95 output 94 control 93 pb17/erxck/spi0_npcs3 in/out input 92 output 91 control 90 pb7/erxer in/out input 89 output 88 control 87 pb12/etxer/tclk0 in/out input 86 output 85 control 84 pb0/etxck/erefck/pck0 pb0/etxck/ere fck/pck0 input 83 output 82 control 81 pb1/etxen pb1/etxen input 80 output 79 control 78 pb2/etx0 pb2/etx0 input 77 output 76 control 75 pb3/etx1 pb3/etx1 input 74 output 73 control 72 pb10/etx2/spi1_npcs1 in/out input 71 output 70 control 69 pb11/etx3/spi1_npcs2 in/out input 68 output 67 control 66 pa19/canrx in/out input 65 output 64 control table 13-2. at91sam7x jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
51 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 63 pa20/cantx in/out input 62 output 61 control 60 pa21/tf/spi1_npcs0 in/out input 59 output 58 control 57 pa22/tk/spi1_spck in/out input 56 output 55 control 54 pb16/ecol/spi1_npcs3 in/out input 53 output 52 control 51 pb4/ecrs in/out input 50 output 49 control 48 pa23/td/spi1_mosi in/out input 47 output 46 control 45 pa24/rd/spi1_miso in/out input 44 output 43 control 42 pa25/rk/spi1_npcs1 in/out input 41 output 40 control 39 pa26/rf/spi1_npcs2 in/out input 38 output 37 control 36 pb18/ef100/adtrg in/out input 35 output 34 control 33 pb19/pwm0/tclk1 in/out input 32 output 31 control table 13-2. at91sam7x jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
52 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30 pb20/pwm1/pck0 in/out input 29 output 28 control 27 pb21/pwm2/pck2 in/out input 26 output 25 control 24 pb22/pwm3/pck2 in/out input 23 output 22 control 21 pb23/tioa0/dcd1 in/out input 20 output 19 control 18 pb24/tiob0/dsr1 in/out input 17 output 16 control 15 pb25/tioa1/dtr1 in/out input 14 output 13 control 12 pb26/tiob1/ri1 in/out input 11 output 10 control 9 pa27drxd/pck3 in/out input 8 output 7 control 6 pa28/dtxd in/out input 5 output 4 control 3 pa29/fiq/spi1_npcs3 in/out input 2 output 1 control table 13-2. at91sam7x jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
53 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 13.5.5 id code register access: read-only version[31:28]: product version number set to 0x0. part number[27:12]: product part number at91sam7x256: 0x5b10 at91sam7x128: 0x5b0f manufacturer identity[11:1] set to 0x01f. bit[0] required by ieee std. 1149.1. set to 0x1. at91sam7x256: jtag id code value is 05b1_003f at91sam7x128: jtag id code value is 05b0_f03f 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1
54 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary
55 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14. reset controller (rstc) 14.1 overview the reset controller (rstc), based on power-on reset cells, handles all the resets of the sys- tem without any external components. it reports which reset occurred last. the reset controller also drives independently or simultaneously the external reset and the peripheral and processor resets. a brownout detection is also available to preven t the processor from falling into an unpredictable state. 14.2 block diagram figure 14-1. reset controller block diagram nrst startup counter proc_nreset wd_fault periph_nreset slck reset state manager reset controller brown_out bod_rst_en rstc_irq nrst manager exter_nreset nrst_out main supply por wdrproc user_reset brownout manager bod_reset
56 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.3 functional description the reset controller is made up of an nrst manager, a brownout manager, a startup counter and a reset state manager. it runs at slow clock and generates the following reset signals: proc_nreset: processor reset line. it also resets the watchdog timer. periph_nreset: affects the whole set of embedded peripherals. nrst_out: drives the nrst pin. these reset signals are asserted by the reset cont roller, either on external events or on soft- ware action. the reset state manager controls the generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager shapes the nrst assertion du ring a programmable ti me, thus controlling external device resets. 14.3.1 nrst manager the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 14-2 shows the block diagram of the nrst manager. figure 14-2. nrst manager 14.3.1.1 nrst signal or interrupt the nrst manager samples the nrst pin at slow clock speed. when the line is detected low, a user reset is reported to the reset state manager. however, the nrst manager can be programmed to not trigger a reset when an assertion of nrst occurs. writing the bit ursten at 0 in rstc_mr disables the user reset trigger. the level of the pin nrst can be read at any ti me in the bit nrstl (nrst level) in rstc_sr. as soon as the pin nrst is asserted, the bit ur sts in rstc_sr is set. this bit clears only when rstc_sr is read. the reset controller can also be programmed to generate an interrupt instead of generating a reset. to do so, the bit urstien in rstc_mr must be written at 1. 14.3.1.2 nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the ?nrst_out? signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertion duration, named externa l_reset_length, lasts external reset timer ursts ursten erstl exter_nreset urstien rstc_mr rstc_mr rstc_mr rstc_sr nrstl nrst_out nrst rstc_irq other interrupt sources user_reset
57 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 2 (erstl+1) slow clock cycles. this gives the approx imate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time compliant with potential external devices connected on the system reset. 14.3.2 brownout manager brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. when vddcore drops below the brownout threshold, the brownout manager requests a brownout re set by asserting the bod_reset signal. the programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose nvm bit in the flash. when the brownout reset is disabled, no reset is performed. instead, the brownout detection is reported in the bit bodsts of rstc_sr. bodsts is set and clears only when rstc_sr is read. the bit bodsts can trigger an interrupt if the bit bodien is set in the rstc_mr. at factory, the brownout reset is disabled. figure 14-3. brownout manager rstc_irq brown_out bod_reset bod_rst_en bodien rstc_mr bodsts rstc_sr other interrupt sources
58 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.3.3 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. 14.3.3.1 power-up reset when vddcore is powered on, the main supply por cell output is filtered with a start-up counter that operates at slow clock. the purpose of this counter is to ensure that the slow clock oscillator is stable before starting up the device. the startup time, as shown in figure 14-4 , is hardcoded to comply wit h the slow clock oscillator startup time. after the startup time, the reset signals are released and the field rsttyp in rstc_sr reports a power-up reset. when vddcore is detected low by the main suppl y por cell, all reset signals are asserted immediately. figure 14-4. power-up reset slck periph_nreset proc_nreset main supply por output nrst (nrst_out) external reset length = 2 cycles startup time mck processor startup = 3 cycles any freq.
59 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.3.3.2 user reset the user reset is entered when a low level is detected on the nrst pin and the bit ursten in rstc_mr is at 1. the nrst inpu t signal is resynchronized with slck to insure proper behav- ior of the system. the user reset is entered as soon as a low level is detected on nrst. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, afte r a two-cycle resynchroniza tion time and a three- cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. how- ever, if nrst does not rise after extern al_reset_length becaus e it is driven low externally, the internal reset lines remain asserted until nrst actually rises. figure 14-5. user reset state slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup = 3 cycles any freq. resynch. 2 cycles rsttyp any xxx resynch. 2 cycles 0x4 = user reset
60 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.3.3.3 brownout reset when the brown_out/bod_reset signal is asserted, the reset state manager immediately enters the brownout reset. in this state, the processo r, the peripheral and the external reset lines are asserted. the brownout reset is left 3 slow clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. an external reset is also triggered. when the processor reset is released, the field rsttyp in rstc_sr is loaded with the value 0x5, thus indicating that the last reset is a brownout reset. figure 14-6. brownout reset state slck periph_nreset proc_nreset brown_out or bod_reset nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x5 = brownout reset resynch. 2 cycles
61 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.3.3.4 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rstc_cr) with the following bits at 1: procrst: writing procrst at 1 resets the processor and the watchdog timer. perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for debug purposes. extrst: writing extrst at 1 asserts low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these com- mands can be performed independently or simultaneously. the software reset lasts 3 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are released when the software reset is left, i.e.; syn- chronously to slck. if extrst is set, the nrst_out signal is asserted depending on the programming of the field erstl. however, the result ing falling edge on nrst does not lead to a user reset. if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. as soon as a software operation is detected, the bit srcmp (software reset command in progress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr ha s no effect. figure 14-7. software reset slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 cycle srcmp in rstc_sr
62 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.3.3.5 watchdog reset the watchdog reset is entered when a watc hdog fault occurs. this state lasts 3 slow clock cycles. when in watchdog reset, assertion of the reset signals depends on the wdrproc bit in wdt_mr: if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nreset si gnal. as the watchdog fault always causes a processor reset if wdrsten is set, the watchd og timer is always reset after a watchdog reset, and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, the watchdog fault has no impact on the reset controller. figure 14-8. watchdog reset only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x2 = watchdog reset
63 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.3.4 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: power-up reset brownout reset watchdog reset software reset user reset particular cases are listed below: when in user reset: ? a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. ? a software reset is impossible, since the processor reset is being activated. when in software reset: ? a watchdog event has priority over the current state. ? the nrst has no effect. when in watchdog reset: ? the processor reset is active and so a software reset cannot be programmed. ? a user reset cannot be entered. 14.3.5 reset controller status register the reset controller status register (rstc_sr) provides several status fields: rsttyp field: this field gives the type of the last reset, as explained in previous sections. srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. nrstl bit: the nrstl bit of the status register gives the level of the nrst pin sampled on each mck rising edge. ursts bit: a high-to-low transition of the nrst pin sets the ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 14-9 ). if the user reset is disabled (ursten = 0) and if the interruption is enabled by the urstien bit in the rstc_mr register, the ursts bit triggers an interrupt. reading the rstc_sr status register resets the ursts bit and clears the interrupt. bodsts bit: this bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). it triggers an interrupt if the bit bodien in the rstc_mr register enables the interrupt. reading the rstc_sr register resets the bodsts bit and clears the interrupt.
64 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 14-9. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1)
65 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.4 reset controller (rstc) user interface table 14-1. reset controller (rstc) register mapping offset register name access reset value 0x00 control register rstc_cr write-only - 0x04 status register rs tc_sr read-only 0x0000_0000 0x08 mode register rstc_mr read/write 0x0000_0000
66 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.4.1 reset controller control register register name: rstc_cr access type: write-only procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????extrstperrst?procrst
67 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.4.2 reset controller status register register name: rstc_sr access type: read-only ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. bodsts: brownout detection status 0 = no brownout high-to-low transition happened since the last read of rstc_sr. 1 = a brownout high-to-low transition has be en detected since the last read of rstc_sr. rsttyp: reset type reports the cause of the last processor reset. r eading this rstc_sr does not reset this field. nrstl: nrst pin level registers the nrst pin level at master clock (mck). srcmp: software reset command in progress 0 = no software command is being performed by the reset controller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????srcmpnrstl 15 14 13 12 11 10 9 8 ????? rsttyp 76543210 ??????bodstsursts rsttyp reset type comments 0 0 0 power-up reset vddcore rising 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor re set required by the software 1 0 0 user reset nrst pin detected low 1 0 1 brownout reset brownout reset occurred
68 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 14.4.3 reset controller mode register register name: rstc_mr access type: read/write ursten: user reset enable 0 = the detection of a low level on the pin nrst does not generate a user reset. 1 = the detection of a low level on the pin nrst triggers a user reset. urstien: user reset interrupt enable 0 = usrts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = usrts bit in rstc_sr at 1 asserts rstc_irq if ursten = 0. bodien: brownout detection interrupt enable 0 = bodsts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = bodsts bit in rstc_sr at 1 asserts rstc_irq. erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????bodien 15 14 13 12 11 10 9 8 ???? erstl 76543210 ???urstien???ursten
69 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 15. real-time timer (rtt) 15.1 overview the real-time timer is built around a 32-bit coun ter and used to count elapsed seconds. it gen- erates a periodic interrupt or/and triggers an alarm on a programmed value. 15.2 block diagram figure 15-1. real-time timer 15.3 functional description the real-time timer is used to count elapsed seconds. it is built around a 32-bit counter fed by slow clock divided by a programmable 16-bit va lue. the value can be programmed in the field rtpres of the real-time mode register (rtt_mr). programming rtpres at 0x00008000 corresponds to feeding the real-time counter with a 1 hz signal (if the slow clock is 32.768 hz). the 32-bit counter can count up to 2 32 seconds, corre- sponding to more than 136 years, then roll over to 0. the real-time timer can also be used as a free -running timer with a lower time-base. the best accuracy is achieved by writing rtpres to 3. programming rtpres to 1 or 2 is possible, but may result in losing status events because the stat us register is cleared two slow clock cycles after read. thus if the rtt is configured to trigger an interrupt, the interrupt occurs during 2 slow clock cycles after reading rtt_sr. to prevent se veral executions of the interrupt handler, the interrupt must be disabled in the interrupt handl er and re-enabled when the status register is clear. slck rtpres rttinc alms 16-bit divider 32-bit counter almv = crtv rtt_mr rtt_vr rtt_ar rtt_sr rttincien rtt_mr 0 10 almien rtt_int rtt_mr set set rtt_sr read rtt_sr reset reset rtt_mr reload rtt_alarm rttrst rtt_mr rttrst
70 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the real-time timer value (crtv) can be read at any time in the register rtt_vr (real-time value register). as this value can be updated asynchronously from the master clock, it is advis- able to read this register twice at the same value to improve accuracy of the returned value. the current value of the counter is compared with the value written in the alarm register rtt_ar (real-time alarm register). if the counter value matches the alarm, the bit alms in rtt_sr is set. the alarm register is set to its maximum value, corresponding to 0xffff_ffff, after a reset. the bit rttinc in rtt_sr is set each time the real-time timer counter is incremented. this bit can be used to start a periodic interrupt, the period being one second when the rtpres is pro- grammed with 0x8000 and slow clock equal to 32.768 hz. reading the rtt_sr status register resets the rttinc and alms fields. writing the bit rttrst in rtt_mr immediately re loads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. figure 15-2. rtt counting prescaler almv almv-1 0 almv+1 0 rtpres - 1 rtt apb cycle read rtt_sr alms (rtt_sr) apb interface mck rttinc (rtt_sr) almv+2 almv+3 ... apb cycle
71 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 15.4 real-time timer (rtt) user interface table 15-1. real-time timer (rtt) register mapping offset register name access reset value 0x00 mode register rtt_mr read/write 0x0000_8000 0x04 alarm register rtt_ar read/write 0xffff_ffff 0x08 value register rtt_vr read-only 0x0000_0000 0x0c status register rtt_sr read-only 0x0000_0000
72 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 15.4.1 real-time timer mode register register name: rtt_mr access type: read/write rtpres: real-time timer prescaler value defines the number of slck periods required to increment the real-time timer. rtpres is defined as follows: rtpres = 0: the prescaler period is equal to 2 16 rtpres 0: the prescaler period is equal to rtpres. almien: alarm interrupt enable 0 = the bit alms in rtt_sr has no effect on interrupt. 1 = the bit alms in rtt_sr asserts interrupt. rttincien: real-time timer increment interrupt enable 0 = the bit rttinc in rtt_sr has no effect on interrupt. 1 = the bit rttinc in r tt_sr asserts interrupt. rttrst: real-time timer restart 1 = reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????rttrstrttincienalmien 15 14 13 12 11 10 9 8 rtpres 76543210 rtpres
73 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 15.4.2 real-time timer alarm register register name: rtt_ar access type: read/write almv: alarm value defines the alarm value (almv+1) compared with the real-time timer. 15.4.3 real-time timer value register register name: rtt_vr access type: read-only crtv: current real-time value returns the current value of the real-time timer. 31 30 29 28 27 26 25 24 almv 23 22 21 20 19 18 17 16 almv 15 14 13 12 11 10 9 8 almv 76543210 almv 31 30 29 28 27 26 25 24 crtv 23 22 21 20 19 18 17 16 crtv 15 14 13 12 11 10 9 8 crtv 76543210 crtv
74 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 15.4.4 real-time timer status register register name: rtt_sr access type: read-only alms: real-time alarm status 0 = the real-time alarm has not occurred since the last read of rtt_sr. 1 = the real-time alarm occurred since the last read of rtt_sr. rttinc: real-time timer increment 0 = the real-time timer has not been incremented since the last read of the rtt_sr. 1 = the real-time timer has been incremented since the last read of the rtt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????rttincalms
75 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 16. periodic interval timer (pit) 16.1 overview the periodic interval timer (pit) provides the operating system?s scheduler interrupt. it is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 block diagram figure 16-1. periodic interval timer 20-bit counter mck/16 piv pit_mr cpiv pit_pivr picnt 12-bit adder 0 0 read pit_pivr cpiv picnt pit_piir pits pit_sr set reset pitien pit_mr pit_irq 1 0 1 0 mck prescaler = ?
76 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 16.3 functional description the periodic interval timer aims at providing pe riodic interrupts for use by operating systems. the pit provides a programmable overflow counter and a reset-on-read feature. it is built around two counters: a 20-bit cpiv counter and a 12-bit picnt counter. both counters work at master clock /16. the first 20-bit cpiv counter increments from 0 up to a programmable overflow value set in the field piv of the mode register (pit_mr). when the counter cpiv reaches this value, it resets to 0 and increments the periodic interval counter, picnt. the status bit pits in the status regis- ter (pit_sr) rises and triggers an interrupt, provided the interrupt is enabled (pitien in pit_mr). writing a new piv value in pit_mr does not reset/restart the counters. when cpiv and picnt values are obtained by reading the periodic interval value register (pit_pivr), the overflow counter (picnt) is rese t and the pits is cleared, thus acknowledging the interrupt. the value of picnt gives the number of periodic intervals elapsed since the last read of pit_pivr. when cpiv and picnt values are obtained by reading the periodic interval image register (pit_piir), there is no effect on the counters cpiv and picnt, nor on the bit pits. for exam- ple, a profiler can read pit_piir without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading pit_pivr. the pit may be enabled/disabled using the pite n bit in the pit_mr register (disabled on reset). the piten bit only becomes effective when the cpiv value is 0. figure 16-2 illustrates the pit counting. after the pit enable bit is re set (piten= 0), the cpiv goes on counting until the piv value is reached, and is then reset. pit restarts counting, only if the piten is set again. the pit is stopped when the core enters debug state.
77 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 16-2. enabling/disabling pit with piten mck prescaler piv piv - 1 0 piten 10 0 15 cpiv 1 restarts mck prescaler 0 1 apb cycle read pit_pivr 0 picnt pits (pit_sr) mck apb interface apb cycle
78 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 16.4 periodic interval time r (pit) user interface table 16-1. periodic interval timer (pit) register mapping offset register name access reset value 0x00 mode register pit_mr read/write 0x000f_ffff 0x04 status register pit_sr read-only 0x0000_0000 0x08 periodic interval value register pit_pivr read-only 0x0000_0000 0x0c periodic interval image register pit_piir read-only 0x0000_0000
79 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 16.4.1 periodic interval timer mode register register name: pit_mr access type: read/write piv: periodic interval value defines the value compared with the primary 20-bit counter of the periodic interval timer (cpiv). the period is equal to (piv + 1). piten: period interval timer enabled 0 = the periodic interval timer is disabled when the piv value is reached. 1 = the periodic interval timer is enabled. pitien: periodic interval timer interrupt enable 0 = the bit pits in pit_sr has no effect on interrupt. 1 = the bit pits in pit_sr asserts interrupt. 16.4.2 periodic interval timer status register register name: pit_sr access type: read-only pits: periodic interval timer status 0 = the periodic interval timer has not reached piv since the last read of pit_pivr. 1 = the periodic interval timer has reached piv since the last read of pit_pivr. 31 30 29 28 27 26 25 24 ??????pitienpiten 23 22 21 20 19 18 17 16 ???? piv 15 14 13 12 11 10 9 8 piv 76543210 piv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????pits
80 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 16.4.3 periodic interval timer value register register name: pit_pivr access type: read-only reading this register clears pits in pit_sr. cpiv: current periodic interval value returns the current value of the periodic interval timer. picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 16.4.4 periodic interval timer image register register name: pit_piir access type: read-only cpiv: current periodic interval value returns the current value of the periodic interval timer. picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
81 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 17. watchdog timer (wdt) 17.1 overview the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 block diagram figure 17-1. watchdog timer block diagram = 0 10 set reset read wdt_sr or reset wdt_fault (to reset controlle r) set reset wdfien wdt_int wdt_mr slck 1/128 12-bit down counter current value wdd wdt_mr <= wdd wv wdrstt wdt_mr wdt_cr reload wdunf wderr reload write wdt_mr wdrsten wdt_mr
82 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 17.3 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it re starts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field wv of the mode register (wdt_mr) . the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wv is 0xfff, corresponding to the maximum value of the counter with the external reset generation enab led (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wdt_mr) if he does not expect to use it or must repro- gram it to meet the maximum watchdog period the application requires. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer with the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer under- flow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reloaded from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the ?wdt_fault? signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in the watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur in a window defined by 0 and wdd in the wdt_mr: 0 wdt wdd; writing wdrstt rest arts the watchdog timer. any attempt to restart the watchdog timer in the range [wdv; wdd] results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the ?wdt_fault? signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarti ng the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow) and wderr (watchdog error) trigger an inter- rupt, provided the bit wdfien is set in the mode register. the signal ?wdt_fault? to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the ?wdt_fault? signal to the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr.
83 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 17-2. watchdog behavior 0 wdv wdd wdt_cr = wdrstt watchdog fault normal behavior watchdog error watchdog underflow fff if wdrsten is 1 if wdrsten is 0 forbidden window permitted window
84 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 17.4 watchdog timer (wdt) user interface 17.4.1 watchdog timer control register register name: wdt_cr access type: write-only wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. table 17-1. watchdog timer (wdt) register mapping offset register name access reset value 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read/write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????wdrstt
85 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 17.4.2 watchdog timer mode register register name: wdt_mr access type: read/write once wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to w dd, writing wdt_cr with wdrs tt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writing wdt_cr with wdrstt = 1 causes a watchdog error. wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer. 31 30 29 28 27 26 25 24 ? ? wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv
86 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 17.4.3 watchdog timer status register register name: wdt_sr access type: read-only wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????wderrwdunf
87 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 18. voltage regulator mode controller (vreg) 18.1 overview the voltage regulator mode controller contains one read/write register, the voltage regulator mode register. its offset is 0x60 with respect to the system controller offset. this register controls the voltage regulator mode. setting pstdby (bit 0) puts the voltage regulator in standby mode or low-power mode. on reset, the pstdby is reset, so as to wake up the voltage regulator in normal mode.
88 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 18.2 voltage regulator power cont roller (vreg) user interface 18.2.1 voltage regulator mode register register name: vreg_mr access type: read/write pstdby: periodic interval value 0 = voltage regulator in normal mode. 1 = voltage regulator in standby mode (low-power mode). table 18-1. voltage regulator power controller register mapping offset register name access reset value 0x60 voltage regulator mode register vreg_mr read/write 0x0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????pstdby
89 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19. memory controller (mc) 19.1 overview the memory controller (mc) manages the asb bus and contro ls accesses requested by the masters, typically the arm7tdmi processor and the peripheral dma controller. it features a bus arbiter, an address decoder, an abort status, a misalignment detector and an embedded flash controller. 19.2 block diagram figure 19-1. memory controller block diagram arm7tdmi processor bus arbiter peripheral dma controller memory controller abort asb abort status address decoder user interface peripheral 0 peripheral 1 internal ram apb apb bridge misalignment detector from master to slave peripheral n embedded flash controller internal flash emac dma
90 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19.3 functional description the memory controller h andles the internal asb bus and arbitrates the accesses of up to three masters. it is made up of: a bus arbiter an address decoder an abort status a misalignment detector an embedded flash controller the mc handles only little-endian mode accesses. the masters work in little-endian mode only. 19.3.1 bus arbiter the memory controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the three masters. the emac has the highest priority; the peripheral dma control- ler has the medium priority; the arm processor has the lowest one. 19.3.2 address decoder the memory controller features an address decoder that first decodes the four highest bits of the 32-bit address bus and defines three separate areas: one 256-mbyte address space for the internal memories one 256-mbyte address space reserved for the embedded peripherals an undefined address space of 3584m bytes representing fourteen 256-mbyte areas that return an abort if accessed figure 19-2 shows the assignment of the 256-mbyte memory areas. figure 19-2. memory areas 0x0000 0000 0x0fff ffff 0x1000 0000 0xefff ffff 0xf000 0000 0xffff ffff 256m bytes 256m bytes 14 x 256mbytes 3,584 mbytes internal memories undefined (abort) peripherals
91 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19.3.2.1 internal memory mapping within the internal memory address space, the address decoder of the memory controller decodes eight more address bits to allocate 1-mbyte address spaces for the embedded memories. the allocated memories are accessed all along the 1-mbyte address space and so are repeated n times within this address space, n equaling 1m bytes divided by the size of the memory. when the address of the access is undefined within the internal memory area, the address decoder returns an abort to the master. figure 19-3. internal memory mapping 19.3.2.2 internal memory area 0 the first 32 bytes of internal memory area 0 contain the arm processor exception vectors, in particular, the reset vector at address 0x0. before execution of the remap command, the on-chip flash is mapped into internal memory area 0, so that the arm7tdmi reaches an executable instruction contained in flash. after the remap command, the internal sram at address 0x0020 0000 is mapped into internal memory area 0. the memory mapped into internal memory area 0 is accessible in both its original loca- tion and at address 0x0. 19.3.3 remap command after execution, the remap command causes the internal sram to be accessed through the internal memory area 0. as the arm vectors (reset, abort, data abort, prefetch abort, undefined instruction, interrupt, and fast interrupt) are mapped from address 0x0 to address 0x20, the remap command allows the user to redefine dynamically these vectors under software control. the remap command is accessible through the me mory controller user in terface by writing the mc_rcr (remap control regi ster) rcb field to one. the remap command can be cancelled by writing the mc_rcr rcb field to one, which acts as a toggling command. this allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset. 256m bytes internal memory area 0 undefined areas (abort) 0x0000 0000 0x000f ffff 0x0010 0000 0x001f ffff 0x0020 0000 0x002f ffff 0x0fff ffff 1m bytes 1m bytes 1m bytes 253m bytes internal memory area 1 internal flash internal memory area 2 internal sram 0x0030 0000
92 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19.3.4 abort status there are two reasons for an abort to occur: access to an undefined address an access to a misaligned address. when an abort occurs, a signal is sent back to all the masters, regardless of which one has gen- erated the access. however, only the arm7tdmi can take an abort signal into account, and only under the condition that it was generating an access. the peripheral dma controller and the emac do not handle the abort input signal. no te that the connections are not represented in figure 19-1 . to facilitate debug or for fault analysis by an operating system, th e memory contro ller integrates an abort status register set. the full 32-bit wide abort address is saved in mc_aasr. parameters of the access are saved in mc_asr and include: the size of the request (field abtsz) the type of the access, whether it is a data read or write, or a code fetch (field abttyp) whether the access is due to accessing an undefined address (bit undadd) or a misaligned address (bit misadd) the source of the access leading to the last abort (bits mst_emac, mst_pdc and mst_arm) whether or not an abort occurred for each master since the last read of the register (bits svmst_emac, svmst_pdc and svmst_arm) unles s this information is loaded in mst bits in the case of a data abort from the processor, the address of the data access is stored. this is useful, as searching for which address generated the abort would require disassembling the instructions and full knowledge of the processor context. in the case of a prefetch abort, the address may have changed, as the prefetch abort is pipe- lined in the arm processor. the arm processor takes the prefetch abort into account only if the read instruction is executed and it is probable th at several aborts have occurred during this time. thus, in this case, it is preferable to use the content of the abort link register of the arm processor. 19.3.5 embedded flash controller the embedded flash controller is added to the memory controller and ensures the interface of the flash block with the 32-bit internal bus. it allows an increase of performance in thumb mode for code fetch with its system of 32-bit buffers. it also manages with the programming, erasing, locking and unlocking sequences th anks to a full set of commands. 19.3.6 misalignment detector the memory controller features a misalignment detector that checks the consistency of the accesses. for each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are checked. if the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. note that the accesses of the arm processor when it is fetching instructions are not checked. the misalignments are generally due to software bugs leading to wrong pointer handling. these bugs are particularly difficult to detect in the debug phase.
93 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary as the requested address is saved in the abort status register and the address of the instruc- tion generating the misalignment is saved in the abort link register of the processor, detection and fix of this kind of software bugs is simplified.
94 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19.4 memory controller (mc) user interface base address : 0xffffff00 table 19-1. memory controller (mc) register mapping offset register name access reset state 0x00 mc remap control register mc_rcr write-only 0x04 mc abort status register mc_asr read-only 0x0 0x08 mc abort address status register mc_aasr read-only 0x0 0x10-0x5c reserved 0x60 efc configuration registers see section 20. ?embedded flash controller (efc)?, on page 99
95 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19.4.1 mc remap control register register name :mc_rcr access type : write-only offset :0x0 rcb: remap command bit 0: no effect. 1: this command bit acts on a toggle basis: writing a 1 altern atively cancels and restores the remapping of the page zero memory devices. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????rcb
96 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19.4.2 mc abort status register register name :mc_asr access type : read-only reset value :0x0 offset :0x04 undadd: undefined address abort status 0: the last abort was not due to the access of an undefined address in the address space. 1: the last abort was due to the access of an undefined address in the address space. misadd: misaligned address abort status 0: the last aborted access was not due to an address misalignment. 1: the last aborted access was due to an address misalignment. abtsz: abort size status abttyp: abort type status mst_emac: emac abort source 0: the last aborted access was not due to the emac. 1: the last aborted access was due to the emac. 31 30 29 28 27 26 25 24 ? ? ? ? ? svmst_arm svmst_pdc svmst_emac 23 22 21 20 19 18 17 16 ? ? ? ? ? mst_arm mst_pdc mst_emac 15 14 13 12 11 10 9 8 ? ? ? ? abttyp abtsz 76543210 ? ? ? ? ? ? misadd undadd abtsz abort size 00 byte 0 1 half-word 10 word 11 reserved abttyp abort type 0 0 data read 0 1 data write 1 0 code fetch 11 reserved
97 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary mst_pdc: pdc abort source 0: the last aborted access was not due to the pdc. 1: the last aborted access was due to the pdc. mst_arm: arm abort source 0: the last aborted access was not due to the arm. 1: the last aborted access was due to the arm. svmst_emac: saved emac abort source 0: no abort due to the emac occurred since the last read of mc_asr or it is notified in the bit mst_emac. 1: at least one abort due to the emac occurred since the last read of mc_asr. svmst_pdc: saved pdc abort source 0: no abort due to the pdc occurred since the last re ad of mc_asr or it is notified in the bit mst_pdc. 1: at least one abort due to the pdc occurred since the last read of mc_asr. svmst_arm: saved arm abort source 0: no abort due to the arm occurred since the last read of mc_asr or it is notified in the bit mst_arm. 1: at least one abort due to the arm occurred since the last read of mc_asr.
98 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 19.4.3 mc abort address status register register name : mc_aasr access type : read-only reset value :0x0 offset :0x08 abtadd: abort address this field contains the address of the last aborted access. 31 30 29 28 27 26 25 24 abtadd 23 22 21 20 19 18 17 16 abtadd 15 14 13 12 11 10 9 8 abtadd 76543210 abtadd
99 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 20. embedded flash controller (efc) 20.0.1 overview the embedded flash controller (efc) is a part of the memory controller and ensures the inter- face of the flash block with the 32-bit internal bus. it increases performance in thumb mode for code fetch with its system of 32-bit buffers. it also manages the programming, erasing, locking and unlocking sequences using a full set of commands. 20.1 functional description 20.1.1 embedded flash organization the embedded flash interfaces directly to the 32- bit internal bus. it is composed of several interfaces: one memory plane organized in several pages of the same size two 32-bit read buffers used for code read optimization (see ?read operations? on page 100 ). one write buffer that manages page programming. the write buffer size is equal to the page size. this buffer is write-only and accessible all along the 1 mbyte address space, so that each word can be written to its final address (see ?write operations? on page 102 ). several lock bits used to protect write and erase operations on lock regions. a lock region is composed of several consecutive pages, and each lock region has its associated lock bit. several general-purpose nvm bits. each bit controls a specific feature in the device. refer to the product definition section to get the gp nvm assignment. the embedded flash size, the page size and the lock region organization are described in the product definition section. table 20-1. product specific lock and general-purpose nvm bits at91sam7x256 at91sam7x128 denomination 3 3 number of general-purpose nvm bits 16 8 number of lock bits
100 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 20-1. embedded flash memory mapping 20.1.2 read operations an optimized controller manages embedded flash reads. a system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing perfor- mance when the processor is running in thumb mode (16-bit instruction set). see figure 20-2 , figure 20-3 and figure 20-4 . this optimization concerns only code fetch and not data. the read operations can be performed with or without wait state. up to 3 wait states can be pro- grammed in the field fws (flash wait state) in the flash mode register mc_fmr (see ?mc flash mode register? on page 110 ). defining fws to be 0 enables the single-cycle access of the embedded flash. the flash memory is accessible through 8-, 16- and 32-bit reads. as the flash block size is smaller than the addr ess space reserved for the internal memory area, the embedded flash wraps around the address space and appears to be repeated within it. lock region 0 lock region (n-1) page 0 page (m-1) start address 32-bit wide flash memory page ( (n-1)*m ) page (n*m-1) lock bit 0 lock region 1 lock bit 1 lock bit n-1
101 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 20-2. code read optimization in thumb mode for fws = 0 note: when fws is equal to 0, all accesse s are performed in a single-cycle access . figure 20-3. code read optimization in thumb mode for fws = 1 note: when fws is equal to 1, in case of sequential reads , all the accesses are performed in a single-cycle access (except for t he first one). flash access buffer (32 bits) master clock arm request (16-bit) code fetch data to arm bytes 0-3 bytes 4-7 bytes 0-3 bytes 0-1 bytes 2-3 bytes 4-5 bytes 6-7 bytes 8-9 bytes 10-11 bytes 12-13 @byte 0 @byte 2 @byte 4 @byte 6 @byte 8 @byte 10 @byte 12 @byte 14 @byte 16 bytes 14-15 bytes 4-7 bytes 8-11 bytes 8-11 bytes 12-15 bytes 16-19 bytes 12-15 flash access buffer (32 bits) master clock arm request (16-bit) code fetch data to arm bytes 0-3 bytes 4-7 bytes 0-3 bytes 2-3 bytes 4-5 bytes 6-7 bytes 8-9 bytes 10-11 @byte 0 @byte 4 @byte 6 @byte 8 @byte 10 @byte 12 @byte 14 bytes 4-7 bytes 8-11 bytes 8-11 bytes 12-15 1 wait state cycle bytes 0-1 1 wait state cycle 1 wait state cycle 1 wait state cycle @byte 2 bytes 12-13
102 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 20-4. code read optimization in thumb mode for fws = 3 note: when fws is equal to 2 or 3, in case of sequential r eads, the first access takes fws cycles, the second access one cycle, the third access fws cycles, the fourth access one cycle, etc. 20.1.3 write operations the internal memory area reserved for the embedded flash can also be written through a write- only latch buffer. write operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area address space and appear to be repeated 1024 times within it. write operations can be prevented by programming the memory protection unit of the product. writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. write operations are performed in the number of wait states equal to the number of wait states for read operations + 1, except for fws = 3 (see ?mc flash mode register? on page 110 ). 20.1.4 flash commands the efc offers a command set to manage programming the memory flash, locking and unlock- ing lock sectors, consecutive programming and locking, and full flash erasing. flash access master clock data to arm 0-1 @byte 0 @2 bytes 0-3 bytes 4-7 bytes 8-11 bytes 12-15 bytes 0-3 2-3 6-7 @4 8-9 10-11 4-5 @8 @12 bytes 4-7 3 wait state cycles buffer (32 bits) arm request (16-bit) code fetch bytes 8-11 3 wait state cycles 3 wait state cycles 3 wait state cycles @6 @10 12-13 table 20-2. set of commands command value mnemonic write page 0x01 wp set lock bit 0x02 slb write page and lock 0x03 wpl clear lock bit 0x04 clb erase all 0x08 ea set general-purpose nvm bit 0x0b sgpb clear general-purpose nvm bit 0x0d cgpb set security bit 0x0f ssb
103 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary to run one of these commands, the field fcmd of the mc_fcr register has to be written with the command number. as soon as the mc_fcr register is written, the frdy flag is automati- cally cleared. once the current command is achieved, then the frdy flag is automatically set. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the mem- ory controller is activated. all the commands are protected by the same keyword, which has to be written in the eight high- est bits of the mc_fcr register. writing mc_fcr with data that does not contain the correct key and/or with an invalid command has no effect on the memory plane; however, the proge flag is set in the mc_fsr register. this flag is automatically cleared by a read access to the mc_fsr register. when the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the locke flag is set in the mc_fsr register. this flag is automatically cleared by a read access to the mc_fsr register.
104 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 20-5. command state chart in order to guarantee valid operations on the fl ash memory, the field flash microsecond cycle number (fmcn) in the flash mode register mc_fmr must be correctly programmed (see ?mc flash mode register? on page 110 ). 20.1.4.1 flash programming several commands can be used to program the flash. the flash technology requires that an erase must be done before programming. the entire memory plane can be erased at the same time, or a page can be automatically erased by clear- ing the nebp bit in the mc_fmr register before writing the command in the mc_fcr register. check if frdy flag set no yes read status: mc_fsr write fcmd and pagenb in mc_fcr check if locke flag set check if frdy flag set no read status: mc_fsr yes yes locking region violation no check if proge flag set yes no bad keyword violation and/or invalid command command successful
105 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary by setting the nebp bit in the mc_fmr register , a page can be programme d in several steps if it has been erased before (see figure 20-6 ). figure 20-6. example of partial page programming: after programming, the page (the whole lock r egion) can be locked to prevent miscellaneous write or erase sequences. the lock bit can be automatically set after page programming using wpl. data to be written are stored in an internal latch buffer. the size of the latch buffer corresponds to the page size. the latch buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it. note: writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. data are written to the latch buffer before the programming command is written to the flash command register mc_fcr. the sequence is as follows: write the full page, at any page address, within the internal memory area address space using only 32-bit access. programming starts as soon as the page number and the programming command are written to the flash command register. the frdy bit in the flash programming status register (mc_fsr) is automatically cleared. when programming is completed, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt was enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register. lock error: the page to be programmed belongs to a locked region. a command must be previously run to unlock the corresponding region. erase all flash programming of the second part of page 7 programming of the third part of page 7 32 bits wide 32 bits wide 32 bits wide 16 words ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ... ca fe ca fe ca fe ca fe ca fe ca fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ca fe ca fe ca fe ca fe ca fe ca fe de ca de ca de ca de ca de ca de ca ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff step 1. step 2. step 3. ... ... ... ... ... ... ... ... ... ... ... (nebp = 1) (nebp = 1) 16 words 16 words 16 words page 7 erased
106 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 20.1.4.2 erase all command the entire memory can be erased if the erase all command (ea) in the flash command regis- ter mc_fcr is written. erase all operation is allowed only if there are no lock bits set. thus, if at least one lock region is locked, the bit locke in mc_fsr rises and the command is cancelled. if the bit locke has been written at 1 in mc_fmr, the interrupt line rises. when programming is complete, the bit frdy bit in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the inter- rupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register. lock error: at least one lock region to be erased is protected. the erase command has been refused and no page has been erased. a clear lock bit command must be executed previously to unlock the corresponding lock regions. 20.1.4.3 lock bit protection lock bits are associated with several pages in the embedded flash memory plane. this defines lock regions in the embedded flash memory plane. they prevent writing/erasing protected pages. after production, the device may have some embedded flash lock regions locked. these locked regions are reserved for a default application. refer to the product definition section for the default embedded flash mapping. locked sectors can be unlocked to be erased and then pro- grammed with another application or other data. the lock sequence is: the flash command register must be written with the following value: (0x5a << 24) | (lockpagenumber << 8 & pagen) | slb lockpagenumber is a page of the corresponding lock region. when locking completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. a programming error, where a bad keyword and/or an invalid command have been written in the mc_fcr register, may be detected in the mc_fsr register after a programming sequence. it is possible to clear lock bits that were set previously. then the locked region can be erased or programmed. the unlock sequence is: the flash command register must be written with the following value: (0x5a << 24) | (lockpagenumber << 8 & pagen) | clb lockpagenumber is a page of the corresponding lock region. when the unlock completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. a programming error, where a bad keyword and/or an invalid command have been written in the mc_fcr register, may be detected in the mc_fsr register after a programming sequence.
107 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the unlock command programs the lock bit to 1; the corresponding bit locksx in mc_fsr reads 0. the lock command programs the lock bit to 0; the corresponding bit locksx in mc_fsr reads 1. note: access to the flash in read mode is permitted when a lock or unlock command is performed. 20.1.4.4 general-purpose nvm bits general-purpose nvm bits do not interfere with the embedded flash memory plane. these gen- eral-purpose bits are dedicated to protect other parts of the product. they can be set (activated) or cleared individually. refer to the product definition section for the general-purpose nvm bit action. the activation sequence is: start the set general purpose bit command (sgpb) by writing the flash command register with the sel command and the number of the general-purpose bit to be set in the pagen field. when the bit is set, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register if the general-purpose bit number is greater than the total number of general-purpose bits, then the command has no effect. it is possible to deactivate a general-purpose nvm bit set previously. the clear sequence is: start the clear general-purpose bit command (cgpb) by writing the flash command register with cgpb and the number of the general-purpose bit to be cleared in the pagen field. when the clear completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register if the number of the general-purpose bit set in the pagen field is greater than the total number of general-purpose bits, then the command has no effect. the clear general-purpose bit command programs the general-purpose nvm bit to 1; the corre- sponding bit gpnvm0 to gpnvmx in mc_fsr reads 0. the set general-purpose bit command programs the general-purpose nvm bit to 0; t he corresponding bit gpnvmx in mc_fsr reads 1. note: access to the flash in read mode is permitt ed when a set, clear or get general-purpose nvm bit command is performed. 20.1.4.5 security bit the goal of the security bit is to prevent external access to th e internal bus system. jtag, fast flash programming and flash serial test interface features are disabled. once set, this bit can be reset only by an external ha rdware erase request to the chip. refer to the produ ct definition
108 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary section for the pin name that controls the erase. in this case, the full memory plane is erased and all lock and general-purpose nvm bits are cleared. the security bit in the mc_fsr is cleared only after these operatio ns. the activation sequence is: start the set security bit command (ssb) by writing the flash command register. when the locking completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. when the security bit is active, the security bit in the mc_fsr is set.
109 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 20.2 embedded flash controll er (efc) user interface the user interface of the efc is integrated within the memory controller with base address: 0xffff ff00. table 20-3. embedded flash controller (efc) register mapping offset register name access reset state 0x60 mc flash mode register mc_fmr read/write 0x0 0x64 mc flash command register mc_fcr write-only ? 0x68 mc flash status register mc_fsr read-only ? 0x6c reserved ? ? ?
110 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 20.2.1 mc flash mode register register name :mc_fmr access type : read/write offset :0x60 frdy: flash ready interrupt enable 0: flash ready does not generate an interrupt. 1: flash ready generates an interrupt. locke: lock error interrupt enable 0: lock error does not generate an interrupt. 1: lock error generates an interrupt. proge: programming error interrupt enable 0: programming error does not generate an interrupt. 1: programming error generates an interrupt. nebp: no erase before programming 0: a page erase is performed before programming. 1: no erase is performed before programming. fws: flash wait state this field defines the number of wait states for read and write operations: fmcn: flash microsecond cycle number before writing non volatile memo ry bits (lock bits, general purpose nvm bit and security bits), this field must be set to the number of master clock cycles in one microsecond. when writing the rest of the flash, this field defines the numb er of master clock cycles in 1.5 microseconds. this number must be rounded up. warning : the value 0 is only allowed for a master clock period superior to 30 microseconds. warning: in order to guarantee valid operations on the flash memory, the field flash microsecond cycle number (fmcn) must be correctly programmed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 fmcn 15 14 13 12 11 10 9 8 ?????? fws 76543210 nebp ? ? ? proge locke ? frdy fws read operations write operations 0 1 cycle 2 cycles 1 2 cycles 3 cycles 2 3 cycles 4 cycles 3 4 cycles 4 cycles
111 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 20.2.2 mc flash command register register name :mc_fcr access type : write-only offset :0x64 fcmd: flash command this field defines the flash commands: 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ?????? pagen 15 14 13 12 11 10 9 8 pag e n 76543210 ???? fcmd fcmd operations 0000 no command. does not raise the programming error status flag in the flash status register mc_fsr. 0001 write page command (wp): starts the programming of the page specified in the pagen field. 0010 set lock bit command (slb): starts a set lock bit sequence of the lo ck region specified in the pagen field. 0011 write page and lock command (wpl): the lock sequence of the lock region associated with the page specified in the field pagen occurs automatically after completion of the programming sequence . 0100 clear lock bit command (clb): starts a clear lock bit sequence of the lock region specified in the pagen field. 1000 erase all command (ea): starts the erase of the entire flash. if at least one page is locked, the command is cancelled. 1011 set general-purpose nvm bit (sgpb): activates the general-purpose nvm bit corresponding to the number specified in the pagen field. 1101 clear general purpose nvm bit (cgpb): deactivates the general-purpose nvm bit corres ponding to the number specified in the pagen field. 1111 set security bit command (ssb): sets security bit. others reserved. raises the programming error status flag in the flash status register mc_fsr.
112 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary pagen: page number note: depending on the command, all the possible unused bits of pagen are meaningless. key: write protection key this field should be written with the value 0x5a to enable the command defined by the bits of the register. if the field is wri t- ten with a different value, the write is not performed and no action is started. command pagen description write page command pagen defines the page number to be written. write page and lock command pagen defines the page number to be written and its associated lock region. erase all command this field is meaningless set/clear lock bit command pagen defines one page number of the lock region to be locked or unlocked. set/clear general purpose nvm bit command pa gen defines the general-purpose bit number. set security bit command this field is meaningless
113 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 20.2.3 mc flash status register register name :mc_fsr access type : read-only offset :0x68 frdy: flash ready status 0: the efc is busy and the application must wait before running a new command. 1: the efc is ready to run a new command. locke: lock error status 0: no programming of at least one locked lock region has happened since the last read of mc_fsr. 1: programming of at least one locked lock regi on has happened since the last read of mc_fsr. proge: programming error status 0: no invalid commands and no bad keywords were written in the flash command register mc_fcr. 1: an invalid command and/or a bad keyword was/were written in the flash command register mc_fcr. security: security bit status 0: the security bit is inactive. 1: the security bit is active. gpnvmx: general-purpose nvm bit status 0: the corresponding general- purpose nvm bit is inactive. 1: the corresponding general-purpose nvm bit is active. locksx: lock region x lock status 0: the corresponding lock region is not locked. 1: the corresponding lock region is locked 31 30 29 28 27 26 25 24 locks15 locks14 locks13 locks1 2 locks11 locks10 locks9 locks8 23 22 21 20 19 18 17 16 locks7 locks6 locks5 locks4 locks3 locks2 locks1 locks0 15 14 13 12 11 10 9 8 ?????gpnvm2gpnvm1gpnvm0 76543210 ? ? ? security proge locke ? frdy mc_fsr, locksx product specific map at91sam7x256 at91sam7x128 denomination 16 8 number of lock bits locks0 locks0 lock region 0 lock status locks1 locks1 lock region 1 lock status locks2 locks2 lock region 2 lock status locks3 locks3 lock region 3 lock status locks4 locks4 lock region 4 lock status locks5 locks5 lock region 5 lock status
114 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary locks6 locks6 lock region 6 lock status locks7 locks7 lock region 7 lock status locks8 ? lock region 8 lock status locks9 ? lock region 9 lock status locks10 ? lock region 10 lock status locks11 ? lock region 11 lock status locks12 ? lock region 12 lock status locks13 ? lock region 13 lock status locks14 ? lock region 14 lock status locks15 ? lock region 15 lock status mc_fsr, locksx product specific map (continued) at91sam7x256 at91sam7x128 denomination
115 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21. fast flash programming interface (ffpi) 21.1 overview the fast flash programming interface provides tw o solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. the parallel interface is fully handshaked and the device is considered to be a standard eeprom. additionally, the parallel protocol offers an optimized access to all t he embedded flash functionalities. the serial inter- face uses the standard ieee 1149.1 jtag protocol. it offers an optimized access to all the embedded flash functionalities. although the fast flash programming mode is a dedicated mode for high volume programming, this mode not designed for in-situ programming. 21.2 parallel fast flash programming 21.2.1 device configuration in fast flash programming mode, the device is in a specific test mode. only a certain set of pins is significant. other pins must be left unconnected. figure 21-1. parallel programming interface ncmd pgmncmd rdy pgmrdy noe pgmnoe nvalid pgmnvalid mode[3:0] pgmm[3:0] data[15:0] pgmd[15:0] xin tst vddio pgmen0 pgmen1 0 - 50mhz vddio vddcore vddio vddpll vddflash gnd gnd vddio pgmen2
116 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.2.2 signal names depending on the mode settings, data is latched in different internal registers. table 21-1. signal description list signal name function type active level comments power vddflash flash power supply power vddio i/o lines power supply power vddcore core power supply power vddpll pll power supply power gnd ground ground clocks xin main clock input. this input can be tied to gnd. in this case, the device is clocked by the internal rc oscillator. input 32khz to 50mhz test tst test mode select input high must be connected to vddio pgmen0 test mode select input high must be connected to vddio pgmen1 test mode select input high must be connected to vddio pgmen2 test mode select input low must be connected to gnd pio pgmncmd valid command available input low pulled-up input at reset pgmrdy 0: device is busy 1: device is ready for a new command output high pulled-up input at reset pgmnoe output enable (active high) input low pulled-up input at reset pgmnvalid 0: data[15:0] is in input mode 1: data[15:0] is in output mode output low pulled-up input at reset pgmm[3:0] specifies data type (see table 21-2 ) input pulled-up input at reset pgmd[15:0] bi-directional data bus input/output pulled-up input at reset table 21-2. mode coding mode[3:0] symbol data 0000 cmde command register 0001 addr0 address register lsbs 0010 addr1 0011 addr2 0100 addr2 address register msbs 0101 data data register default idle no register
117 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary when mode is equal to cmde, then a new command (strobed on data[15:0] signals) is stored in the command register. 21.2.3 entering programming mode the following algorithm puts the devi ce in parallel programming mode: apply gnd, vddio, vddcore, vddflash and vddpll. apply xin clock within t por_reset if an external clock is available. wait for t por_reset start a read or write handshaking. note: after reset, the device is clocked by the internal rc oscillator. before clearing rdy signal, if an external clock ( > 32 khz) is connected to xin, then the device switches on the external clock. else, xin input is not considered. a highe r frequency on xin speeds up the programmer handshake. 21.2.4 programmer handshaking an handshake is defined for read and write operations. when the device is ready to start a new operation (rdy signal set), the programmer star ts the handshake by clearing the ncmd signal. the handshaking is achieved once nc md signal is high and rdy is high. table 21-3. command bit coding data[15:0] symbol command executed 0x0011 read read flash 0x0012 wp write page flash 0x0022 wpl write page and lock flash 0x0032 ewp erase page and write page 0x0042 ewpl erase page and write page then lock 0x0013 ea erase all 0x0014 slb set lock bit 0x0024 clb clear lock bit 0x0015 glb get lock bit 0x0034 sfb set general purpose nvm bit 0x0044 cfb clear general purpose nvm bit 0x0025 gfb get general purpose nvm bit 0x0054 sse set security bit 0x0035 gse get security bit 0x002f rram read memory 0x001f wram write memory 0x001e gve get version
118 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.2.4.1 write handshaking for details on the write handshaking sequence, refer to figure 21-2 and table 21-4 . figure 21-2. parallel programming timing, write sequence 21.2.4.2 read handshaking for details on the read handshaking sequence, refer to figure 21-3 and table 21-5 . ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 table 21-4. write handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latches mode and data input 3 waits for rdy low clears rdy signal input 4 releases mode and data signals executes command and polls ncmd high input 5 sets ncmd signal executes command and polls ncmd high input 6 waits for rdy high sets rdy input
119 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 21-3. parallel programming timing, read sequence 21.2.5 device operations several commands on the flash memory are available. these commands are summarized in table 21-3 on page 117 . each command is driven by the programmer through the parallel inter- face running several read/write handshaking sequences. when a new command is executed, the previous one is automatically achieved. thus, chaining a read command after a write automatically flushes the load buffer in the flash. ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 6 7 9 8 addr adress in z data out 10 11 xin 12 13 table 21-5. read handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latch mode and data input 3 waits for rdy low clears rdy signal input 4 sets data signal in tristate waits for noe low input 5 clears noe signal tr i s t a t e 6 waits for nvalid low sets data bus in output mode and outputs the flash contents. output 7 clears nvalid signal output 8 reads value on data bus waits for noe high output 9 sets noe signal output 10 waits for nvalid high sets data bus in input mode x 11 sets data in ouput mode sets nvalid signal input 12 sets ncmd signal waits for ncmd high input 13 waits for rdy high sets rdy signal input
120 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.2.5.1 flash read command this command is used to read the contents of the flash memory. the read command can start at any valid address in the memory plane and is optimized for consecutive reads. read hand- shaking can be chained; an internal address buffer is automatically increased. 21.2.5.2 flash write command this command is used to write the flash contents. the flash memory plane is organized into several pages. data to be written are stored in a load buffer that corresponds to a flash memory page. the load buffer is automatically flushed to the flash: before access to any page other than the current one when a new command is validated (mode = cmde) the write page command (wp) is optimized for consecutive wr ites. write handshaking can be chained; an internal address buffer is automatically increased. table 21-6. read command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde read 2 write handshaking addr0 32-bit memory address first byte 3 write handshaking addr1 32-bit flash address 4 write handshaking addr2 32-bit flash address 5 write handshaking addr3 32-bit flash address last byte 6 read handshaking data *memory address++ 7 read handshaking data *memory address++ ... ... ... ... n write handshaking addr0 32-bit memory address first byte n+1 write handshaking addr1 32-bit flash address n+2 write handshaking addr2 32-bit flash address n+3 write handshaking addr3 32-bit flash address last byte n+4 read handshaking data *memory address++ n+5 read handshaking data *memory address++ ... ... ... ... table 21-7. write command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde wp or wpl or ewp or ewpl 2 write handshaking addr0 32-bit memory address first byte 3 write handshaking addr1 32-bit flash address 4 write handshaking addr2 32-bit flash address 5 write handshaking addr3 32-bit flash address last byte 6 write handshaking data *memory address++
121 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the flash command write page and lock (wpl) is equivalent to the flash write command. however, the lock bit is automatically set at the end of the flash write operation. as a lock region is composed of several pages, the programmer writes to the first pages of the lock region using flash write commands and writes to the last page of the lock region using a flash write and lock command. the flash command erase page and write (ewp) is equivalent to the flash write command. however, before programming the load buffer, the page is erased. the flash command erase page and write the lock (ewpl) combines ewp and wpl commands. 21.2.5.3 flash full erase command this command is used to erase the flash memory planes. all lock regions must be unlocked before the full erase command by using the clb command. otherwise, the erase command is aborted and no page is erased. 21.2.5.4 flash lock commands lock bits can be set using wpl or ewpl co mmands. they can also be set by using the set lock command (slb) . with this command, several lock bits can be activated. a bit mask is pro- vided as argument to the command. when bit 0 of t he bit mask is set, then the first lock bit is activated. in the same way, the clear lock command (clb) is used to clear lock bits. all the lock bits are also cleared by the ea command. 7 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 32-bit memory address first byte n+1 write handshaking addr1 32-bit flash address n+2 write handshaking addr2 32-bit flash address n+3 write handshaking addr3 32-bit flash address last byte n+4 write handshaking data *memory address++ n+5 write handshaking data *memory address++ ... ... ... ... table 21-7. write command (continued) step handshake sequence mode[3:0] data[15:0] table 21-8. full erase command step handshake sequen ce mode[3:0] data[15:0] 1 write handshaking cmde ea 2 write handshaking data 0
122 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary lock bits can be read using get lock bit command (glb) . the n th lock bit is active when the bit n of the bit mask is set.. 21.2.5.5 flash general-purpose nvm commands general-purpose nvm bits (gp nvm bits) can be set using the set fuse command (sfb) . this command also activates gp nvm bits. a bit mask is provided as argument to the command. when bit 0 of the bit mask is set, then the first gp nvm bit is activated. in the same way, the clear fuse command (cfb) is used to clear general-purpose nvm bits. all the general-purpose nvm bits are also cleared by the ea command. the general-purpose nvm bit is deactived when the corresponding bit in the pattern value is set to 1. general-purpose nvm bits can be read using the get fuse bit command (gfb) . the n th gp nvm bit is active when bit n of the bit mask is set.. table 21-9. set and clear lock bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde slb or clb 2 write handshaking data bit mask table 21-10. get lock bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde glb 2 read handshaking data lock bit mask status 0 = lock bit is cleared 1 = lock bit is set table 21-11. set/clear gp nvm command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde sfb or cfb 2 write handshaking data gp nvm bit pattern value table 21-12. get gp nvm bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde gfb 2 read handshaking data gp nvm bit mask status 0 = gp nvm bit is cleared 1 = gp nvm bit is set
123 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.2.5.6 flash security bit command a security bit can be set using the set security bit command (sse). once the security bit is active, the fast flash programming is disabled. no other command can be run. an event on the erase pin can erase the security bit once th e contents of the flash have been erased. 21.2.5.7 memory read command this command ( rram ) is used to perform a read access to any memory location. the read command can start at any valid address in the memory plane and is optimized for consecutive reads. read handshaking can be chained; an internal address buffer is automatically increased. 21.2.5.8 memory write command this command is used to perform a write access to any memory location. the memory write command (wram) is optimized for consecutive writes. write handshaking can be chained; an internal address buffer is automatically increased. table 21-13. set security bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde sse 2 write handshaking data 0 table 21-14. read command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde rram 2 write handshaking addr0 32-bit memory address first byte 3 write handshaking addr1 32-bit flash address 4 write handshaking addr2 32-bit flash address 5 write handshaking addr3 32-bit flash address last byte 6 read handshaking data *memory address++ 7 read handshaking data *memory address++ ... ... ... ... n write handshaking addr0 32-bit memory address first byte n+1 write handshaking addr1 32-bit flash address n+2 write handshaking addr2 32-bit flash address n+3 write handshaking addr3 32-bit flash address last byte n+4 read handshaking data *memory address++ n+5 read handshaking data *memory address++ ... ... ... ...
124 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.2.5.9 get version command the get version (gve) command retrieves the version of the ffpi interface. table 21-15. write command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde wram 2 write handshaking addr0 32-bit memory address first byte 3 write handshaking addr1 32-bit flash address 4 write handshaking addr2 32-bit flash address 5 write handshaking addr3 32-bit flash address last byte 6 write handshaking data *memory address++ 7 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 32-bit memory address first byte n+1 write handshaking addr1 32-bit flash address n+2 write handshaking addr2 32-bit flash address n+3 write handshaking addr3 32-bit flash address last byte n+4 write handshaking data *memory address++ n+5 write handshaking data *memory address++ ... ... ... ... table 21-16. get version command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde gve 2 write handshaking data version
125 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.3 serial fast flash programming the serial fast flash programming interface is based on ieee std. 1149.1 ?standard test access port and boundary-scan architecture?. refe r to this standard for an explanation of terms used in this chapter and for a description of the tap controller states. in this mode, data read/written from/to the embedded flash of the device are transmitted through the jtag interface of the device. 21.3.1 device configuration in serial fast flash programming mode, the device is in a specific test mode. only a distinct set of pins is significant. other pins must be left unconnected. figure 21-4. serial programming tdi tdo tms tck xin tst vddio pgmen0 pgmen1 0-50mhz vddio vddcore vddio vddpll vddflash gnd vddio gnd pgmen2 table 21-17. signal description list signal name function type active level comments power vddflash flash power supply power vddio i/o lines power supply power vddcore core power supply power vddpll pll power power supply power gnd ground ground clocks xin main clock input. this input can be tied to gnd. in this case, the device is clocked by the internal rc oscillator. input 32 khz to 50 mhz
126 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.3.2 entering serial programming mode the following algorithm puts the device in serial programming mode: apply gnd, vddio, vddcore, vddflash and vddpll. apply xin clock within t por_reset + 32(t sclk ) if an external clock is available. wait for t por_reset . reset the tap controller clocking 5 tck pulses with tms set. shift 0x2 into the ir register ( ir is 4 bits long, lsb first) without going through the run-test- idle state. shift 0x2 into the dr register ( dr is 4 bits long, lsb first) without going through the run- test-idle state. shift 0xc into the ir register ( ir is 4 bits long, lsb first) without going through the run-test- idle state. note: after reset, the device is clocked by the internal rc oscillator. before clearing rdy signal, if an external clock ( > 32 khz) is connected to xin, t hen the device will switch on the external clock. else, xin input is not considered. an high er frequency on xin speeds up the programmer handshake. test tst test mode select input high must be connected to vddio. pgmen0 test mode select input high must be connected to vddio pgmen1 test mode select input high must be connected to vddio pgmen2 test mode select input low must be connected to gnd jtag tck jtag tck input - pulled-up input at reset tdi jtag test data in input - pulled-up input at reset tdo jtag test data out output - tms jtag test mode select input - pulled-up input at reset table 21-17. signal description list (continued) signal name function type active level comments table 21-18. reset tap controller and go to select-dr-scan tdi tms tap controller state x1 x1 x1 x1 x 1 test-logic reset x 0 run-test/idle xt 1 select-dr-scan
127 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.3.3 read/write handshake two registers of the device are accessible through the jtag: debug comms control register: dccr debug comms data register: dcdr access to these registers is done through the ta p 38-bit dr register comprising a 32-bit data field, a 5-bit address field and a read/write bit. the data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. a register is read by scanning its address into th e address field and 0 into the read/write bit, going through the update-dr tap state, then scanning out the data. the 32-bit data field is ignored. figure 21-5. tap 8-bit dr register a read or write takes place when the tap controller enters update-dr state. the address of the debug comms control register is 0x04. the address of the debug comms data register is 0x05. the debug comms control register is read-only and allows synchronized handshaking between the processor and the debugger. bit 1 (w): denotes whether the programmer can read a data through the debug comms data register. if the device is busy w = 0, then the programmer must poll until w = 1. bit 0 (r): denotes whether the programmer can send data from the debug comms data register. if r = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. 21.3.4 device operations several commands on the flash memory are available. these commands are summarized in table 21-3 on page 117 . commands are run by the programmer through the serial interface that is reading and writing the debug comms registers. 21.3.4.1 flash read command this command is used to read the flash contents. the memory map is accessible through this command. memory is seen as an array of words (32-bit wide). the read command can start at tdi tdo 4 0 r/w address 31 data 0 address decoder debug comms control register debug comms control register 32 5
128 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary any valid address in the memory plane. this address must be word-aligned . the address is automatically incremented. 21.3.4.2 flash write command this command is used to write the flash contents. the address transmitted must be a valid flash address in the memory plane. the flash memory plane is organized into several pages. data to be written is stored in a load buffer that corresponds to a flash memory page. the load buffer is automatically flushed to the flash: before access to any page than the current one at the end of the number of words transmitted the write page command (wp) is optimized for consecutive wr ites. write handshaking can be chained; an internal address buffer is automatically increased. flash write page and lock command (wpl) is equivalent to the flash write command. how- ever, the lock bit is automatically set at the end of the flash write operation. as a lock region is composed of several pages, the programmer writes to the first pages of the lock region using flash write commands and writes to the last page of the lock region using a flash write and lock command. flash erase page and write command (ewp) is equivalent to the flash write command. how- ever, before programming the load buffer, the page is erased. flash erase page and write the lock command (ewpl) combines ewp and wpl commands. table 21-19. read command read/write dr data write (number of words to read) << 16 | read write address read memory [address] read memory [address+4] ... ... read memory [address+(number of words to read - 1)* 4] table 21-20. write command read/write dr data write (number of words to write) << 16 | (wp or wpl or ewp or ewpl) write address write memory [address] write memory [address+4] write memory [address+8] write memory [address+(number of words to write - 1)* 4]
129 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.3.4.3 flash full erase command this command is used to erase the flash memory planes. all lock bits must be deactivated before using the full erase command. this can be done by using the clb command. 21.3.4.4 flash lock commands lock bits can be set using wpl or ewpl co mmands. they can also be set by using the set lock command (slb) . with this command, several lock bits can be activated at the same time. bit 0 of bit mask corresponds to the first lock bit and so on. in the same way, the clear lock command (clb) is used to clear lock bits. all the lock bits can also be cleared by the ea command. lock bits can be read using get lock bit command (glb) . when a bit set in the bit mask is returned, then the corresponding lock bit is active. 21.3.4.5 flash general-purpose nvm commands general-purpose nvm bits (gp nvm) can be set with the set fuse command (sfb) . using this command, several gp nvm bits can be activated at the same time. bit 0 of bit mask corre- sponds to the first fuse bit and so on. in the same way, the clear fuse command (cfb) is used to clear gp nvm bits. all the general- purpose nvm bits are also cleared by the ea command. table 21-21. full erase command read/write dr data write ea table 21-22. set and clear lock bit command read/write dr data write slb or clb write bit mask table 21-23. get lock bit command read/write dr data write glb read bit mask table 21-24. set and clear general-purpose nvm bit command read/write dr data write sfb or cfb write bit mask
130 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary gp nvm bits can be read using get fuse bit command (gfb) . when a bit set in the bit mask is returned, then the corresponding fuse bit is set. 21.3.4.6 flash security bit command security bits can be set using set security bit command (sse). once the security bit is active, the fast flash programming is disabled. no othe r command can be run. only an event on the erase pin can erase the security bit once th e contents of the flash have been erased. 21.3.4.7 memory read command this command is used to perform a read access to any memory location. the read command can start at any valid address in the memory plane and is optimized for consecutive reads. an internal address buffer is automatically increased. 21.3.4.8 memory write command this command is used to perform a write access to any memory location. the memory wrire command (wram) is optimized for consecutive writes. an internal address buffer is automatically increased. table 21-25. get general-purpose nvm bit command read/write dr data write gfb read bit mask table 21-26. set security bit command read/write dr data write sse table 21-27. read command read/write dr data write (number of words to read) << 16 | rram write address read memory [address] read memory [address+4] ... ... read memory [address+(number of words to read - 1)* 4] table 21-28. write command read/write dr data write (number of words to write) << 16 | (wram) write address write memory [address]
131 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 21.3.4.9 get version command the get version (gve) command retrieves the version of the ffpi interface. write memory [address+4] write memory [address+8] write memory [address+(number of words to write - 1)* 4] table 21-28. write command read/write dr data table 21-29. get version command read/write dr data write gve read version
132 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary
133 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 22. at91sam boot program 22.1 description the boot program integrates different programs permitting download and/or upload into the different memories of the product. first, it initializes the debug unit serial port (dbgu) and the usb device port. sam-ba ? boot is then executed. it waits for transactions either on the usb device, or on the dbgu serial port. 22.2 flow diagram the boot program implements the algorithm in figure 22-1 . figure 22-1. boot program algorithm flow diagram 22.3 device initialization initialization follows the steps described below: 1. fiq initialization 1. stack setup for arm supervisor mode 2. setup the embedded flash controller 3. external clock detection 4. main oscillator frequency detection if no external clock detected 5. switch master clock on main oscillator 6. copy code into sram 7. c variable initialization 8. pll setup: pll is initialized to generate a 48 mhz clock necessary to use the usb device 9. disable of the watchdog and enable of the user reset 10. initialization of the usb device port 11. jump to sam-ba boot sequence (see ?sam-ba boot? on page 133 ) 22.4 sam-ba boot the sam-ba boot principle is to: ? wait for usb device enumeration ? execute the autobaudrate sequence in parallel (see figure 22-2 ) device setup autobaudrate sequence run sam-ba boot run sam-ba boot or usb enumeration successful
134 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 22-2. autobaudrate flow diagram ? once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in table 22-1 . write commands: write a byte ( o ), a halfword ( h ) or a word ( w ) to the target. ? address : address in hexadecimal. ? value : byte, halfword or word to write in hexadecimal. ? output : ?>?. device setup character '0x80' received ? no ye s character '0x80' received ? no ye s character '#' received ? ye s run sam-ba boot send character '>' no 1st measurement 2nd measurement test communication uart operational table 22-1. commands available through the sam-ba boot command action argument(s) example o write a byte address, value# o 200001,ca# o read a byte address,# o 200001,# h write a half word address, value# h 200002,cafe# h read a half word address,# h 200002,# w write a word address, value# w 200000,cafedeca# w read a word address,# w 200000,# s send a file address,# s 200000,# r receive a file address, nbofbytes# r 200000,1234# g go address# g 200200# v display version no argument v #
135 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary read commands: read a byte ( o ), a halfword ( h ) or a word ( w ) from the target. ? address : address in hexadecimal ? output : the byte, halfword or word read in hexadecimal following by ?>? send a file ( s ): send a file to a specified address ? address : address in hexadecimal ? output : ?>?. note: there is a time-out on this command which is reached when the prompt ?>? appears before the end of the command execution. receive a file ( r ): receive data into a file from a specified address ? address : address in hexadecimal ? nbofbytes : number of bytes in hexadecimal to receive ? output : ?>? go ( g ): jump to a specified address and execute the code ? address : address to jump in hexadecimal ? output : ?>? get version ( v ): return the sam-ba boot version ? output : ?>? 22.4.1 dbgu serial port communication is performed through the dbgu serial port initialized to 115200 baud, 8, n, 1. the send and receive file commands use the xmodem protocol to communicate. any termi- nal performing this protocol can be used to send the application file to the target. the size of the binary file to send depends on the sram size embedded in the product. in all cases, the size of the binary file must be lower than the sram size because the xmodem protocol requires some sram memory to work. 22.4.2 xmodem protocol the xmodem protocol supported is the 128-byte l ength block. this protocol uses a two-char- acter crc-16 to guar antee detectio n of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: <255-blk #><--128 da ta bytes--> in which: ? = 01 hex ? = binary number, starts at 01, increments by 1, and wraps 0ffh to 00h (not to 01) ? <255-blk #> = 1?s complement of the blk#. ? = 2 bytes crc16 figure 22-3 shows a transmission using this protocol.
136 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 22-3. xmodem transfer example 22.4.3 usb device port a 48 mhz usb clock is necessary to use the usb device port. it has been programmed ear- lier in the device initialization procedure with pllb configuration. the device uses the usb communi cation device class (cdc) drivers to take advantage of the installed pc rs-232 software to talk over the usb. the cdc class is implemented in all releases of windows ? , from windows 98se to windows xp. the cdc document, available at www.usb.org, describes a way to implement devices such as isdn modems and virtual com ports. the vendor id is atmel?s vendor id 0x03eb. th e product id is 0x6124 . these references are used by the host operating system to mount the correct driver. on windows systems, the inf files contain the correspondence between vendor id and product id. atmel provides an inf example to see the devi ce as a new serial port and also provides another custom driver used by the sam-ba app lication: atm6124.sys. refer to the document ?usb basic application?, literature number 6123, for more details. 22.4.3.1 enumeration process the usb protocol is a master/slave protocol. this is the host that starts the enumeration send- ing requests to the device through the control endpoint. the device handles standard requests as defined in the usb specification. host device soh 01 fe data[128] crc crc c ack soh 02 fd data[128] crc crc ack soh 03 fc data[100] crc crc ack eot ack table 22-2. handled standard requests request definition get_descriptor returns the current device configuration value. set_address sets the device address for all future device access. set_configuration sets the device configuration. get_configuration returns the curr ent device configuration value.
137 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the device also handles some class requests defined in the cdc class. unhandled requests are stalled. 22.4.3.2 communication endpoints there are two communication endpoints and endpoint 0 is used for the enumeration process. endpoint 1 is a 64-byte bulk out endpoint an d endpoint 2 is a 64-byte bulk in endpoint. sam-ba boot commands are sent by the host through the endpoint 1. if required, the mes- sage is split by the host into several data payloads by the host driver. if the command requires a response, the host can send in transactions to pick up the response. 22.5 hardware and software constraints sam-ba boot copies itself in the sram and uses a block of internal sram for variables and stacks. the remaining available size for the user code is 57344 bytes for at91sam7x256 and 24576 bytes for at91sam7x128. usb requirements: ? 18.432 mhz quartz get_status returns status for the specified recipient. set_feature used to set or enable a specific feature. clear_feature used to clear or disable a specific feature. table 22-3. handled class requests request definition set_line_coding configures dte rate, stop bits, parity and number of character bits. get_line_coding requests current dte rate, stop bits, parity and number of character bits. set_control_line_state rs-232 signal used to tell the dce device the dte device is now present. table 22-2. handled standard requests (continued) request definition table 22-4. user area addresses device start address end address size (bytes) at91sam7x256 0x202000 0x210000 57344 at91sam7x128 0x202000 0x208000 24576 table 22-5. pins driven during boot program execution peripheral pin pio line dbgu drxd pa27 dbgu dtxd pa28
138 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary
139 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23. peripheral dma controller (pdc) 23.1 overview the peripheral dma controller (pdc) transfers data between on-chip serial peripherals such as the uart, usart, ssc, spi, mci and the on- and off-chip memories. using the peripheral dma contoller avoids processor intervention and removes the processor interrupt-handling overhead. this significantly reduces the number of clock cycles requ ired for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient. the pdc channels are implemented in pairs, each pair being dedicated to a particular periph- eral. one channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each uart, usart, ssc and spi. the user interface of a pdc channel is integrated in the memory space of each peripheral. it contains: a 32-bit memory pointer register a 16-bit transfer count register a 32-bit register for next memory pointer a 16-bit register for next transfer count the peripheral triggers pdc transfers usin g transmit and receive signals. when the pro- grammed data is transferred, an end of trans fer interrupt is generated by the corresponding peripheral. 23.2 block diagram figure 23-1. block diagram control pdc channel 0 pdc channel 1 thr rhr control status & control peripheral peripheral dma controller memory controller
140 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.3 functional description 23.3.1 configuration the pdc channels user interface enables the user to configure and control the data transfers for each channel. the user interface of a pdc channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. per peripheral, it contains four 32-bit pointer registers (rpr, rnpr, tpr, and tnpr) and four 16-bit counter re gisters (rcr, rncr, tcr, and tncr). the size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. the memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. it is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. the pdc has dedicated sta- tus registers which indicate if the transfer is enabl ed or disabled for each channel. the status for each channel is located in the peripheral status register. transfers can be enabled and/or dis- abled by setting txten/txtdis and rxten/rxtd is in pdc transfer control register. these control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads. the pdc sends status flags to the peripheral vi sible in its status-register (endrx, endtx, rxbuff, and txbufe). endrx flag is set when the periph_rcr register reaches zero. rxbuff flag is set when both pe riph_rcr and periph_rncr reach zero. endtx flag is set when the per iph_tcr register reaches zero. txbufe flag is set when both pe riph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register. 23.3.2 memory pointers each peripheral is connected to the pdc by a receiver data channel and a transmitter data channel. each channel has an internal 32-bit memory pointer. each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory). depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively for peripheral transfers. if a memory pointer is reprogrammed while the pdc is in operation, the transfer address is changed, and the pdc performs transfers using the new address. 23.3.3 transfer counters there is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. these counters are decremented after each data transfer. when the counter reaches zero, the transfer is complete and the pdc stops transfer- ring data. if the next counter register is equal to zero, the pdc disables the trigger while activating the related peripheral end flag.
141 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary if the counter is reprogrammed while the pdc is operating, the number of transfers is updated and the pdc counts transfers from the new value. programming the next counter/pointer register s chains the buffers. the counters are decre- mented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the next counter/pointer are loaded into the counter/pointer registers in order to re-enable the triggers. for each channel, two status bits indicate the end of the current buffer (endrx, entx) and the end of both current and next buffer (rxbuff, txbufe). these bits are directly mapped to the peripheral status register and can trigger an interrupt request to the aic. the peripheral end flag is automatically cleared when one of the counter-registers (counter or next counter regi ster) is written. note: when the next counter register is loaded into the counter register, it is set to zero. 23.3.4 data transfers the peripheral triggers pdc transfers using transmit (txrdy) and receive (rxrdy) signals. when the peripheral receives an external characte r, it sends a receive ready signal to the pdc which then requests access to the system bus. when access is granted, the pdc starts a read of the peripheral receive holding register (rhr) and then triggers a write in the memory. after each transfer, the relevant pdc memory pointer is incremented and the number of trans- fers left is decremented. when the memory bl ock size is reached, a signal is sent to the peripheral and the transfer stops. the same procedure is followed, in reverse, for transmit transfers. 23.3.5 priority of pdc transfer requests the peripheral dma controller handles transfer requests from the channel according to priori- ties fixed for each product.these prioriti es are defined in the product datasheet. if simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. if transfer requests are not simultaneous, they are treated in the order they occurred. requests from the receivers are handled first and then followed by transmitter requests.
142 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.4 peripheral dma controll er (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the peripheral desired (dbgu, usart, ssc, spi, mci etc). table 23-1. peripheral dma controller (pdc) register mapping offset register register name read/write reset 0x100 receive pointer register periph (1) _rpr read/write 0x0 0x104 receive counter register periph_rcr read/write 0x0 0x108 transmit pointer register periph_tpr read/write 0x0 0x10c transmit counter register periph_tcr read/write 0x0 0x110 receive next pointer register periph_rnpr read/write 0x0 0x114 receive next counter register periph_rncr read/write 0x0 0x118 transmit next pointer register periph_tnpr read/write 0x0 0x11c transmit next counter register periph_tncr read/write 0x0 0x120 pdc transfer control register periph_ptcr write-only - 0x124 pdc transfer status r egister periph_ptsr read-only 0x0
143 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.4.1 pdc receive pointer register register name: periph _ rpr access type: read/write rxptr: receive pointer address address of the next receive transfer. 23.4.2 pdc receive counter register register name: periph _ rcr access type: read/write rxctr: receive counter value number of receive transfers to be performed. 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr
144 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.4.3 pdc transmit pointer register register name: periph _ tpr access type: read/write txptr: transmit pointer address address of the transmit buffer. 23.4.4 pdc transmit counter register register name: periph _ tcr access type: read/write txctr: transmit counter value txctr is the size of the transmit transfer to be performed. at zero, the peripheral dma transfer is stopped. 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txctr 76543210 txctr
145 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.4.5 pdc receive next pointer register register name: periph _ rnpr access type: read/write rxnptr: receive next pointer address rxnptr is the address of the next buffer to fill with received data when th e current buffer is full. 23.4.6 pdc receive next counter register register name: periph _ rncr access type: read/write rxncr: receive next counter value rxncr is the size of the next buffer to receive. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxncr 76543210 rxncr
146 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.4.7 pdc transmit next pointer register register name: periph _ tnpr access type: read/write txnptr: transmit next pointer address txnptr is the address of the next buffer to transmit when the current buffer is empty. 23.4.8 pdc transmit next counter register register name: periph _ tncr access type: read/write txncr: transmit next counter value txncr is the size of the next buffer to transmit. 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txncr 76543210 txncr
147 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.4.9 pdc transfer control register register name: periph_ptcr access type: write - only rxten: receiver transfer enable 0 = no effect. 1 = enables the receiver pdc transfer requests if rxtdis is not set. rxtdis: receiver transfer disable 0 = no effect. 1 = disables the receiver pdc transfer requests. txten: transmitter transfer enable 0 = no effect. 1 = enables the transmitter pdc transfer requests. txtdis: transmitter transfer disable 0 = no effect. 1 = disables the transmitter pdc transfer requests 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txtdistxten 76543210 ??????rxtdisrxten
148 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 23.4.10 pdc transfer status register register name: periph _ ptsr access type: read-only rxten: receiver transfer enable 0 = receiver pdc transfer requests are disabled. 1 = receiver pdc transfer requests are enabled. txten: transmitter transfer enable 0 = transmitter pdc transfer requests are disabled. 1 = transmitter pdc transfer requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten
149 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24. advanced interrupt controller (aic) 24.1 overview the advanced interrupt controller (aic) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to sub- stantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupts or external inter- rupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. the fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt. 24.2 block diagram figure 24-1. block diagram 24.3 application block diagram figure 24-2. description of the application block aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler
150 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.4 aic detailed block diagram figure 24-3. aic detailed block diagram 24.5 i/o line description 24.6 product dependencies 24.6.1 i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio control- lers. depending on the features of the pio controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. this is not applicable when the pio controller used in the product is transparent on the input path. 24.6.2 power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to wake up the processor without asserting the interr upt line of the processor, thus providing syn- chronization of the processor on an event. 24.6.3 interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock table 24-1. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input
151 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the interrupt source 1 is always located at system interrupt. this is the result of the or-wiring of the system peripheral interrupt lines, such as the system timer, the real time clock, the power management controller and the memory controller. when a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. this is performed by reading suc- cessively the status registers of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines . the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peri pheral). consequently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31.
152 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.7 functional description 24.7.1 interrupt source control 24.7.1.1 interrupt source mode the advanced interrupt controller independently programs each interrupt source. the src- type field of the corresponding aic_smr (source mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level-sen- sitive modes, or in positive edge-triggered or negative edge-triggered modes. 24.7.1.2 interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register). this set of registers conducts enabling or disabling in one instruc- tion. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. 24.7.1.3 interrupt clearing and setting all interrupt sources programmed to be edge-triggered (including the fiq in source 0) can be individually set or cleared by writing respectively the aic_iscr and aic_iccr registers. clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect. the clear operation is perfunctory, as the softwa re must perform an acti on to reinitialize the ?memorization? circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vector register) is read. only the interrupt source being detected by the aic as the current interrupt is affected by this operation. ( see ?priority controller? on page 155. ) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered uniquely as an fiq source. ( see ?fast forcing? on page 159. ) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. 24.7.1.4 interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see ?priority controller? on page 155 ) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems.
153 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.7.1.5 internal interrupt source input stage figure 24-4. internal interrupt source input stage 24.7.1.6 external interrupt source input stage figure 24-5. external interrupt source input stage edge detector clear set source i aic_ipr aic_imr aic_iecr aic_idcr aic_iscr aic_iccr fast interrupt controller or priority controller ff level/ edge aic_smri (srctype) edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/low aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller
154 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.7.2 interrupt latencies global interrupt latencies depend on several parameters, including: the time the software masks the interrupts. occurrence, either at the processor level or at the aic level. the execution time of the instruction in progress when the interrupt occurs. the treatment of higher priority interrupts and the resynchronization of the hardware signals. this section addresses only the hardware resync hronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the pro- cessor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 24.7.2.1 external interrupt edge triggered source figure 24-6. external interrupt edge triggered source 24.7.2.2 external interrupt level sensitive source figure 24-7. external interrupt level sensitive source maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge) maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq
155 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.7.2.3 internal interrupt edge triggered source figure 24-8. internal interrupt edge triggered source 24.7.2.4 internal interrupt level sensitive source figure 24-9. internal interrupt level sensitive source 24.7.3 normal interrupt 24.7.3.1 priority controller an 8-level priority controller drives the nirq line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writ- ing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt condition occurs, as defined by the srctype field of the aic_svr (source vector register), the nirq line is a sserted. as a new interrupt condition might have happened on other interrupt sources since the nirq has been asserted, the priority controller determines the current interrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending and enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. the nirq line can be asserted only if an interrupt cond ition occurs on an in terrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active
156 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling . 24.7.3.2 interrupt nesting the priority controller utilizes interr upt nesting in order for the high priority interrup t to be handled during the service of lower priority interrupts. this requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. when an interrupt of a higher priority happens during an already occurring interrupt service rou- tine, the nirq line is re-asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the aic_eoicr is written. the aic is equipped with an 8-leve l wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 24.7.3.3 interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the reg- isters aic_svr1 to aic_svr31 (source vector register 1 to 31). when the processor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the cur- rent interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus acces- sible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. however, it is strongly recommended to port the operating system on at91 products by support- ing the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical interr upt to transfer the execution on a specific very fast handler and not onto the operating system?s general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral han- dling) to be handled efficiently and independently of the application running under an operating system. 24.7.3.4 interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt mode s and the associated status bits. it is assumed that:
157 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit ?i? of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_i rq, the current value of the program coun ter is loaded in the interrupt link register (r14_irq) and the program counter (r15) is loaded with 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, dec- rementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_ivr. reading the aic_ivr has the following effects: ? sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. ? de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. ? automatically clears the interrupt, if it has been programmed to be edge-triggered. ? pushes the current level and the current interrupt number on to the stack. ? returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branc hing to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruction sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the ?i? bit in cpsr, allowing re- assertion of the nirq to be taken into account by the core. this can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can th en proceed as required, savi ng the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current leve l will restart the sequence from step 1. note: if the interrupt is programmed to be level sensitiv e, the source of the interrupt must be cleared dur- ing this phase. 7. the ?i? bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indi- cate to the aic that the current interrupt is finished. this causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the inter- rupt sequence does not immediately start because the ?i? bit is set in the core. spsr_irq is restored. fina lly, the saved value of the link regi ster is restored directly into the pc. this has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the cpsr with the stored spsr, masking or unmasking the interrupts depending on the state saved in spsr_irq. note: the ?i? bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an interrupt when the mask instruction was in terrupted. hence, when spsr is restored, the mask instruction is comple ted (interrupt is masked).
158 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.7.4 fast interrupt 24.7.4.1 fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. the interrupt sour ce 0 is generally connected to an fiq pin of the product, either directly or through a pio controller. 24.7.4.2 fast interrupt control the fast interrupt logic of the aic has no priority controller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it reads what has been written. the fi eld srctype of aic_smr0 enable s programming the fast inter- rupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register) respectively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whet her the fast interrupt is enabled or disabled. 24.7.4.3 fast interrupt vectoring the fast interrupt handler address can be stored in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast vector reg- ister). this offers a way to branch in one single instruction to the interr upt handler, as aic_fvr is mapped at the absolute address 0xffff f104 and thus accessible from the arm fast inter- rupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction it loads the value read in aic_fvr in its program counter, thus branching the execution on the fast interrupt handler. it also automatically per- forms the clear of the fast interrupt source if it is programmed in edge-triggered mode. 24.7.4.4 fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt modes and associated status bits. assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted, if the bit "f" of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in the following cycle, during fetch at address 0x20, the arm core ad justs r14_fiq, decre- menting it by four. 2. the arm core enters fiq mode.
159 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. re ading the aic_fvr has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding interrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save regis- ters r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being exec uted before, loading the cpsr with the spsr and masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the "f" bit in spsr is significant. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instru ction was interrupted. hence wh en the spsr is restored, the interrupted instruction is completed (fiq is masked). another way to handle the fast interrupt is to map the interrupt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. 24.7.4.5 fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any normal interrupt source on the fast interrupt controller. fast forcing is enabled or disabl ed by writing to the fast forcing enable register (aic_ffer) and the fast forcing disable register (aic_ff dr). writing to these re gisters results in an update of the fast forcing status register (aic _ffsr) that controls the feature for each inter- nal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages. when fast forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt s ource is still active but the source c annot trigger a normal interrupt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level- sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core. the fast forcing feature does not affect the source 0 pending bit in the interrupt pending reg- ister (aic_ipr). the fast interrupt vector register (aic_fvr) reads the contents of the source vector register 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not
160 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the interrupt cl ear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues operating normally and becomes one of the fast interrupt sources. figure 24-10. fast forcing 24.7.5 protect mode the protect mode permits reading the interrupt vector register without performing the associ- ated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ic e, stops the applica- tions and updates the opened windows, it might read the aic user interface and thus the ivr. this has undesirable consequences: if an enabled interrupt with a higher priority than the current one is pending, it is stacked. if there is no enabled pending interrupt, the spurious vector is returned. in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and caus e the application to enter an undesired state. this is avoided by using the protect mode. writing dbgm in aic_dcr (debug control register) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must write (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager nfiq nirq read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31.
161 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary not stop the processor between the read and the write of aic_ivr of the interrupt service routine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following opera- tions within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. 5. acknowledges the interrupt. however, while the protect mode is activated, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr write has no effect and can be removed to optimize the code. 24.7.6 spurious interrupt the advanced interrupt controller features protec tion against spurious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: an external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the progr ammer must store the address of a spurious interrupt handler in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt. 24.7.7 general interrupt mask the aic features a general interrupt mask bit to prevent interrupts from reaching the processor. both the nirq and the nfiq lines are driven to thei r inactive state if the bit gmsk in aic_dcr (debug control register) is set. however, this mask does not prevent waking up the processor if it has entered idle mode. this function facilitates synchronizi ng the processor on a next event and, as soon as the event occurs, performs su bsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution.
162 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8 advanced interrupt controll er (aic) user interface 24.8.1 base address the aic is mapped at the address 0xffff f000 . it has a total 4-kbyte addressing space. this permits the vectoring feature, as the pc-relative load/store instructions of the arm processor support only an 4-kbyte offset. note: 1. the reset value of this register depends on the level of the external interrupt source. all other sources are cleared at reset, thus not pending. table 24-2. advanced interrupt controller (aic) register mapping offset register name access reset value 0000 source mode register 0 aic_smr0 read/write 0x0 0x04 source mode register 1 aic_smr1 read/write 0x0 --- --- --- --- --- 0x7c source mode register 31 aic_smr31 read/write 0x0 0x80 source vector register 0 aic_svr0 read/write 0x0 0x84 source vector register 1 aic_svr1 read/write 0x0 --- --- --- --- --- 0xfc source vector register 31 aic_svr31 read/write 0x0 0x100 interrupt vector register aic_ivr read-only 0x0 0x104 fast interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status register aic_isr read-only 0x0 0x10c interrupt pending register aic_ipr read-only 0x0 (1) 0x110 interrupt mask register aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 reserved --- --- --- 0x11c reserved --- --- --- 0x120 interrupt enable command register aic_iecr write-only --- 0x124 interrupt disable command register aic_idcr write-only --- 0x128 interrupt clear command register aic_iccr write-only --- 0x12c interrupt set command register aic_iscr write-only --- 0x130 end of interrupt command register aic_eoicr write-only --- 0x134 spurious interrupt vector register aic_spu read/write 0x0 0x138 debug control register aic_dcr read/write 0x0 0x13c reserved --- --- --- 0x140 fast forcing enable register aic_ffer write-only --- 0x144 fast forcing disable r egister aic_ffdr write-only --- 0x148 fast forcing status register aic_ffsr read-only 0x0
163 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.2 aic source mode register register name: aic_smr0..aic_smr31 access type: read/write reset value: 0x0 prior: priority level programs the priority level for all sources except fiq source (source 0). the priority level can be between 0 (lowest) and 7 (highest). the priority level is not used for the fi q in the related smr register aic_smrx. srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? srctype ? ? prior srctype internal interrupt sources external interrupt sources 0 0 high level sensitive low level sensitive 0 1 positive edge triggered negative edge triggered 1 0 high level sensitive high level sensitive 1 1 positive edge triggered positive edge triggered
164 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.3 aic source vector register register name: aic_svr0..aic_svr31 access type: read/write reset value: 0x0 vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. 24.8.4 aic interrupt vector register register name: aic_ivr access type: read-only reset value: 0 irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current interrupt number when the interrupt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv
165 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.5 aic fiq vector register register name: aic_fvr access type: read-only reset value: 0 fiqv: fiq vector register the fiq vector register contains the vector programmed by the user in the source vector register 0. when there is no fast interrupt, the fast interrupt vector register reads the value stored in aic_spu. 24.8.6 aic interrupt status register register name: aic_isr access type: read-only reset value: 0 irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? irqid
166 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.7 aic interrupt pending register register name: aic_ipr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. 24.8.8 aic interrupt mask register register name: aic_imr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
167 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.9 aic core interrupt status register register name: aic_cisr access type: read-only reset value: 0 nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 24.8.10 aic interrupt enable command register register name: aic_iecr access type: write-only fiq, sys, pid2-pid3: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????nirqnifq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
168 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.11 aic interrupt disable command register register name: aic_idcr access type: write-only fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 24.8.12 aic interrupt clear command register register name: aic_iccr access type: write-only fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
169 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.13 aic interrupt set command register register name: aic_iscr access type: write-only fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 24.8.14 aic end of interrupt command register register name: aic_eoicr access type: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
170 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.15 aic spurious interrupt vector register register name: aic_spu access type: read/write reset value: 0 siqv: spurious interrupt vector register the user may store the address of a spurious interrupt handler in this register. the written value is returned in aic_ivr in case of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 24.8.16 aic debug control register register name: aic_debug access type: read/write reset value: 0 prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. 31 30 29 28 27 26 25 24 siqv 23 22 21 20 19 18 17 16 siqv 15 14 13 12 11 10 9 8 siqv 76543210 siqv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????gmskprot
171 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.17 aic fast forcing enable register register name: aic_ffer access type: write-only sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. 24.8.18 aic fast forcing disable register register name: aic_ffdr access type: write-only sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
172 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 24.8.19 aic fast forcing status register register name: aic_ffsr access type: read-only sys, pid2-pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
173 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 25. clock generator 25.1 description the clock generator is made up of 1 pll, a main oscilla tor, and an rc oscillator. it provides the following clocks: slck, the slow clock, which is the only permanent clock within the system mainck is the output of the main oscillator pllck is the output of the divider and pll block the clock generator user interface is embedded within the power management controller one and is described in section 26.9 . however, the clock generator registers are named ckgr_. 25.2 slow clock rc oscillator the slow clock is the output of the rc oscillator and is the only clock considered permanent in a system that includes the power management controller. it is mandatory in the operations of the pmc. the user has to take the possible drifts of the rc oscillator into account. more details are given in the dc characteristics section of the product datasheet. 25.3 main oscillator figure 25-1 shows the main oscillator block diagram. figure 25-1. main oscillator blockd iagram 25.3.1 main oscillator connections the clock generator integrates a main oscillator that is designed for a 3 to 20 mhz funda- mental crystal. the typical crys tal connection is illustrated in figure 25-2 . the 1 k ? resistor is only required for crystals with frequencies lowe r than 8 mhz. the oscillator contains 25 pf capacitors on each xin and xout pin. consequently, cl1 and cl2 can be removed when a xin xout moscen main oscillator counter oscount moscs mainck main clock main clock frequency counter mainf mainrdy slck slow clock main oscillator
174 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary crystal with a load capacitance of 12.5 pf is used . for further details on the electrical charac- teristics of the main oscillato r, see the dc characteristics se ction of the product datasheet. figure 25-2. typical crystal connection 25.3.2 main oscillator startup time the startup time of the main oscillator is given in the dc characteristi cs section of the product datasheet. the startup time depends on the crystal frequency and decreases when the fre- quency rises. 25.3.3 main oscillator control to minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. the software enables or disables the main os cillator so as to reduc e power cons umption by clearing the moscen bit in the main oscillator register (ckgr_mor). when disabling the main oscilla tor by clearing the moscen bit in ckgr_mor, the moscs bit in pmc_sr is automatically clear ed, indicating the main clock is off. when enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the star tup time of the oscillator. th is startup time depends on the crystal frequency connecte d to the main oscillator. when the moscen bit and the oscount are written in ckgr_mor to enable the main oscillator, the moscs bit in pmc_sr (status register) is cleared and the counter starts counting down on the slow clock divided by 8 from the oscount value. since the oscount value is coded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscs bit is se t, indicating that the main clock is valid. set- ting the moscs bit in pmc_imr can trigger an interrupt to the processor. 25.3.4 main clock frequency counter the main oscillator features a main clock fr equency counter that provides the quartz fre- quency connected to the main oscillator. generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. the main clock frequency counter starts incrementing at the main clock speed after the next rising edge of the slow clock as soon as the main oscillator is stable, i.e., as soon as the moscs bit is set. then, at the 16th falling edge of slow clock, the mainrdy bit in ckgr_mcfr (main clock frequency register) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gives the number of main clock 1k xin xout gnd c l2 c l1
175 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary cycles during 16 periods of slow clock, so t hat the frequency of the crystal connected on the main oscillator ca n be determined. 25.3.5 main oscillator bypass the user can input a clock on the device instead of connecting a crystal. in this case, the user has to provide the external clock signal on the xi n pin. the input characteristics of the xin pin under these conditions are given in the product electrical characteristics section. the program- mer has to be sure to set the oscbypass bit to 1 and the moscen bit to 0 in the main osc register (ckgr_mor) for the external clock to operate properly. 25.4 divider and pll block the pll embeds an input divider to increase the accuracy of the resulting clock signals. how- ever, the user must respect the pll minimum input frequency when programming the divider. figure 25-3 shows the block diagram of the divider and pll block. figure 25-3. divider and pll block diagram 25.4.1 pll filter the pll requires connection to an external second-order filter through the pllrc pin. figure 25-4 shows a schematic of these filters. figure 25-4. pll capacitors and resistors values of r, c1 and c2 to be connected to the pllrc pin must be calculated as a function of the pll input frequency, the pll output frequency and the phase margin. a trade-off has to be found between output signal overshoot and startup time. divider pllrc div pll mul pllcount lock out slck mainck pllck pll counter gnd c1 c2 pll pllrc r
176 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 25.4.2 divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when a divider field (div) is set to 0, the output of the corresponding divider and the p ll output is a continuous signal at level 0. on reset, each div field is set to 0, thus the corresponding pll input clock is set to 0. the pll allows multiplication of the divider?s outputs. the pll clock signal has a frequency that depends on the respective source signal frequency and on the parameters div and mul. the factor applied to the source signal frequency is (mul + 1)/div. when mul is written to 0, the corresponding pll is disabled and its power consumption is saved. re-enabling the pll can be performed by writing a value higher than 0 in the mul field. whenever the pll is re-enabled or one of its parameters is changed, the lock bit in pmc_sr is automatically cleared. the values written in the pllcount field in ckgr_pllr are loaded in the pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an inter- rupt to the processor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllcount field. the transient time depends on the pll filter. the initial state of the pll and its target frequency can be calculated using a specific tool pro- vided by atmel.
177 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26. power management controller (pmc) 26.1 description the power management controller (pmc) opti mizes power consumption by controlling all system and user peripheral clocks. the pmc enab les/disables the clock inputs to many of the peripherals and the arm processor. the power management controller provides the following clocks: mck, the master clock, programmable from a few hundred hz to the maximum operating frequency of the device. it is available to the modules running permanently, such as the aic and the memory controller. processor clock (pck), switched off wh en entering processor in idle mode. peripheral clocks, typically mck, provided to the embedded peripherals (usart, ssc, spi, twi, tc, mci, etc.) and independently controllable. in order to reduce the number of clock names in a product, the peripheral cloc ks are named mck in the product datasheet. udp clock (udpck), required by usb device port operations. programmable clock outputs can be selected from the clocks provided by the clock generator and driven on the pckx pins. 26.2 master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. select- ing the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the pll. the master clock controller is made up of a clock selector and a prescaler. the master clock selection is made by writi ng the css field (clock source selection) in pmc_mckr (master clock register). the prescale r supports the division by a power of 2 of the selected clock between 1 and 64. the pres field in pmc_mckr programs the prescaler. each time pmc_mckr is written to define a ne w master clock, the mckrdy bit is cleared in pmc_sr. it reads 0 until the master clock is established. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high- speed clock to a lower one to inform the software when the change is actually done. figure 26-1. master clock controller slck master clock prescaler mck pres css mainck pllck to the processor clock controller (pck) pmc_mckr pmc_mckr
178 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.3 processor clock controller the pmc features a processor clock controller (pck) that implements the processor idle mode. the processor clock can be enabled and disabled by writing the system clock enable (pmc_scer) and system clock disable registers (pmc_scdr). the status of this clock (at least for debug purpose) can be read in the system clock status register (pmc_scsr). the processor clock pck is enabled after a re set and is automatically re-enabled by any enabled interrupt. the processor idle mode is achieved by disabling the processor clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. when the processor clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 26.4 usb clock controller the usb source clock is the pll output. if using the usb, the user must program the pll to generate a 48 mhz, a 96 mhz or a 192 mhz signal with an accuracy of 0.25% depending on the usbdiv bit in ckgr_pllr. when the pll output is stable, i.e., the lock bit is set: the usb device clock can be enabled by setting the udp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the udp bit in pmc_scdr. the udp bit in pmc_scsr gives the activity of this clock. the usb device port require both the 48 mhz signal and the master clock. the master clock may be controlled via the peripheral clock controller. figure 26-2. usb clock controller 26.5 peripheral clock controller the power management controller controls t he clocks of each embedded peripheral by the way of the peripheral clock controller. the user can individually enable and disable the mas- ter clock on the peripherals by writing into the peripheral clock enable (pmc_pcer) and peripheral clock disable (pmc_pcdr) registers. th e status of the peripheral clock activity can be read in the peripheral clock status register (pmc_pcsr). when a peripheral clock is disabled, the clock is immediately stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peripheral, it is recommended that the system software wait until the periph- eral has executed its last programmed operation before disabling the clock. this is to avoid data corruption or erroneous behavior of the system. usb source clock udp clock (udpck) udp usbdiv divider /1,/2,/4
179 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the bit number within the peripheral clock co ntrol registers (pmc_pcer, pmc_pcdr, and pmc_pcsr) is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 26.6 programmable clock output controller the pmc controls 4 signals to be output on external pins pckx. each signal can be indepen- dently programmed via the pmc_pckx registers. pckx can be independently selected between the slow clock, the pll output and the main clock by writing the css field in pmc_pckx. ea ch output signal can also be divided by a power of 2 between 1 and 64 by writing the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writing 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respec tively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). moreover, like the pck, a status bit in pmc_sr indicates that the programmable clock is actually what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disabl e the programmable clock before any configura- tion change and to re-enable it after the change is actually performed. 26.7 programming sequence 1. enabling the main oscillator: the main oscillator is enabled by setting the moscen field in the ckgr_mor register. in some cases it may be advantageous to define a start-up time. this can be achieved by writing a value in the oscount field in the ckgr_mor register. once this register has been correctly configured, the user must wait for moscs field in the pmc_sr register to be set. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to moscs has been enabled in the pmc_ier register. code example: write_register(ckgr_mor,0x00000701) start up time = 8 * oscount / slck = 56 slow clock cycles. so, the main oscillator will be enabled (moscs bit set) after 56 slow clock cycles. 2. checking the main oscilla tor frequency (optional): in some situations the user may need an accurate measure of the main oscillator fre- quency. this measure can be accomp lished via the ckgr_mcfr register. once the mainrdy field is set in ckgr_mcfr register, the user may read the mainf field in ckgr_mcfr register. this provides the number of main clock cycles within six- teen slow clock cycles.
180 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 3. setting pll and divider: all parameters needed to configure pll and the divider are located in the ckgr_pllr register. the div field is used to control divider itself. a value between 0 and 255 can be pro- grammed. divider output is divider input divided by div parameter. by default div parameter is set to 0 which means that divider is turned off. the out field is used to select the pll b output frequency range. the mul field is the pll multiplier factor. this parameter can be programmed between 0 and 2047. if mul is set to 0, pll will be turn ed off, otherwise the pll output fr equency is pll input frequency mult iplied by (mul + 1). the pllcount field specifies the number of slow clock cycles before lock bit is set in the pmc_sr register after ckgr_pllr register has been written. once the pmc_pll register has been written, the user must wait for the lock bit to be set in the pmc_sr register. this can be done either by polling the status re gister or by waiting the interrupt line to be raised if the associated interrupt to lock has been enabled in the pmc_ier register. all parameters in ckgr_p llr can be programmed in a single write operation. if at some stage one of the following parameters, mul, div is modified, lock bit will go low to indicate that pll is not ready yet. when pll is locked, lock will be set again. the user is constrained to wait for lock bit to be set before using the pll output clock. the usbdiv field is used to control the addition al divider by 1, 2 or 4, which generates the usb clock(s). code example: write_register(ckgr_pllr,0x00040805) if pll and divider are enabled, the pll input cl ock is the main clock. pll output clock is pll input clock multiplied by 5. once ckgr _pllr has been written, lock bit will be set after eight slow clock cycles. 4. selection of master clock and processor clock the master clock and the processor clock are configurable via the pmc_mckr register. the css field is used to select the master cl ock divider source. by default, the selected clock source is slow clock. the pres field is used to control the master clock prescaler. the user can choose between different values (1, 2, 4, 8, 16, 32, 64). master clock output is prescaler input divided by pres parameter. by default, pres parameter is set to 1 which means that master clock is equal to slow clock. once pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done eith er by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register.
181 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary all parameters in pmc_mckr can be programmed in a single write operation. if at some stage one of the following para meters, css or pres, is modified, the mckrdy bit will go low to indicate that the master clock and the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if pllx clock was selected as the master clock and the user decides to modify it by writing in ckgr_pllr, the mckrdy flag will go low while pll is unlocked. once pll is locked again, lock goes high and mckrdy is set. while pll is unlocked, the mast er clock selection is automatically changed to main clock. for further information, see section 26.8.2 . ?clock switching waveforms? on page 183 . code example: write_register(pmc_mckr,0x00000011) the master clock is main clock divided by 16. the processor clock is the master clock. 5. selection of programmable clocks programmable clocks are controlled vi a registers; pmc_scer, pmc_scdr and pmc_scsr. programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. depending on the system used, 4 programmable clocks can be enabled or disabled. the pmc_scsr provides a clear indication as to which programma- ble clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css field is used to select the programmable clock divider source. four clock options are available: main clock, slow clock, pllck. by default, the clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). programmable clock output is prescaler input divided by pres parameter. by default, the pres parameter is set to 1 which means that master clock is equal to slow clock. once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrained to wait for the pckrdyx bit to be set in the pmc_sr register . this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all para meters in pmc_pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. code example:
182 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary write_register(pmc_pck0,0x00000015) programmable clock 0 is main clock divided by 32. 6. enabling peripheral clocks once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers pmc_pcer and pmc_pcdr. depending on the system used, 15 peripheral clocks can be enabled or disabled. the pmc_pcsr provides a clear view as to which peripheral clock is enabled. note: each enabled peripheral clock corresponds to master clock. code examples: write_register(pmc_pcer,0x00000110) peripheral clocks 4 and 8 are enabled. write_register(pmc_pcdr,0x00000010) peripheral clock 4 is disabled.
183 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.8 clock switching details 26.8.1 master clock switching timings table 26-1 gives the worst case timings required for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. 26.8.2 clock switching waveforms figure 26-3. switch master clock from slow clock to pll clock table 26-1. clock switching timings (worst case) from main clock slck pll clock to main clock ? 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pllx clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck slow clock lock mckrdy master clock write pmc_mckr pll clock
184 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 26-4. switch master clo ck from main clock to slow clock figure 26-5. change pll programming slow clock main clock mckrdy master clock write pmc_mckr main clock main clock pll clock lock mckrdy master clock write ckgr_pllr
185 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 26-6. programmable clock output programming pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected
186 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9 power management contro ller (pmc) user interface table 26-2. register mapping offset register name access reset value 0x0000 system clock enable register pmc_scer write-only ? 0x0004 system clock disable register pmc_scdr write-only ? 0x0008 system clock status register pmc _scsr read-only 0x01 0x000c reserved ? ? ? 0x0010 peripheral clock enable register pmc _pcer write-only ? 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0 0x001c reserved ? ? ? 0x0020 main oscillator register ckgr_mor read/write 0x0 0x0024 main clock frequency register ckgr_mcfr read-only 0x0 0x0028 reserved ? ? ? 0x002c pll register ckgr_pllr read/write 0x3f00 0x0030 master clock register pmc_mckr read/write 0x0 0x0034 application clock register pmc_ackr read/write 0x0 0x0038 reserved ? ? ? 0x003c reserved ? ? ? 0x0040 programmable clock 0 register pmc_pck0 read/write 0x0 0x0044 programmable clock 1 register pmc_pck1 read/write 0x0 ... ... ... ... ... 0x0060 interrupt enable register pmc_ier write-only -- 0x0064 interrupt disable register pmc_idr write-only -- 0x0068 status register pmc_sr read-only 0x08 0x006c interrupt mask register pmc_imr read-only 0x0 0x0070 - 0x00fc reserved ? ? ?
187 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.1 pmc system clock enable register register name: pmc_scer access type: write-only pck: processor clock enable 0 = no effect. 1 = enables the processor clock. udp: usb device port clock enable 0 = no effect. 1 = enables the 48 mhz clock of the usb device port. pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udp??????pck
188 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.2 pmc system clock disable register register name: pmc_scdr access type: write-only pck: processor clock disable 0 = no effect. 1 = disables the processor clock. this is used to enter teh processor in idle mode. udp: usb device port clock disable 0 = no effect. 1 = disables the 48 mhz clock of the usb device port. pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udp??????pck
189 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.3 pmc system clock status register register name: pmc_scsr access type: read-only pck: processor clock status 0 = the processor clock is disabled. 1 = the processor clock is enabled. udp: usb device port clock status 0 = the 48 mhz clock (udpck) of th e usb device port is disabled. 1 = the 48 mhz clock (udpck) of the usb device port is enabled. pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udp??????pck
190 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.4 pmc peripheral clock enable register register name: pmc_pcer access type: write-only pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. note: programming the control bits of the peripheral id that ar e not implemented has no effect on the behavior of the pmc. 26.9.5 pmc peripheral clock disable register register name: pmc_pcdr access type: write-only pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - - 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
191 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.6 pmc peripheral clock status register register name: pmc_pcsr access type: read-only pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
192 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.7 pmc clock generator main oscillator register register name: ckgr_mor access type: read/write moscen: main oscillator enable a crystal must be connected between xin and xout. 0 = the main oscillator is disabled. 1 = the main oscillator is enabl ed. oscbypass must be set to 0. when moscen is set, the moscs flag is set once the main oscillator startup time is achieved. oscbypass: oscillator bypass 0 = no effect. 1 = the main oscillator is bypassed . moscen must be set to 0. an extern al clock must be connected on xin. when oscbypass is set, th e moscs flag in pmc_sr is automatically set. clearing moscen and oscbypass bits allows resetting the moscs flag. oscount: main oscillator start-up time specifies the number of slow clock cycles multip lied by 8 for the main o scillator start-up time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 oscount 76543210 ??????oscbypassmoscen
193 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.8 pmc clock generator main clock frequency register register name: ckgr_mcfr access type: read-only mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. mainrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled pr eviously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????mainrdy 15 14 13 12 11 10 9 8 mainf 76543210 mainf
194 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.9 pmc clock generator pll register register name: ckgr_pllr access type: read/write possible limitations on pll input frequencies and multiplier factors should be checked before using the pmc. div: divider pllcount: pll counter specifies the number of slow clock cycles before the lo ck bit is set in pmc_sr after ckgr_pllr is written. out: pll clock frequency range mul: pll multiplier 0 = the pll is deactivated. 1 up to 2047 = the pll clock frequency is the pll input frequency multiplied by mul+ 1. usbdiv: divider for usb clock 31 30 29 28 27 26 25 24 ? ? usbdiv ? mul 23 22 21 20 19 18 17 16 mul 15 14 13 12 11 10 9 8 out pllcount 76543210 div div divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the selected clock divided by div. out pll clock frequency range 0 0 refer to the dc characteristics section of the product datasheet 01reserved 1 0 refer to the dc characteristics section of the product datasheet 11reserved usbdiv divider for usb clock(s) 0 0 divider output is pll clock output. 0 1 divider output is pll clock output divided by 2. 1 0 divider output is pll clock output divided by 4. 1 1 reserved.
195 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.10 pmc master clock register register name: pmc_mckr access type: read/write css: master clock selection pres: master clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 10reserved 1 1 pll clock is selected. pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved
196 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.11 pmc programmable clock register register name: pmc_pckx access type: read/write css: master clock selection pres: programmable clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 10reserved 1 1 pll clock is selected pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved
197 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.12 pmc interrupt enable register register name: pmc_ier access type: write-only moscs: main oscillator status interrupt enable lock: pll lock interrupt enable mckrdy: master clock ready interrupt enable pckrdyx: programmable clock ready x interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs
198 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.13 pmc interrupt disable register register name: pmc_idr access type: write-only moscs: main oscillator status interrupt disable lock: pll lock interrupt disable mckrdy: master clock ready interrupt disable pckrdyx: programmable clock ready x interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs
199 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.14 pmc status register register name: pmc_sr access type: read-only moscs: moscs flag status 0 = main oscillator is not stabilized. 1 = main oscillator is stabilized. lock: pll lock status 0 = pll is not locked 1 = pll is locked. mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs
200 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.9.15 pmc interrupt mask register register name: pmc_imr access type: read-only moscs: main oscillator status interrupt mask lock: pll lock interrupt mask mckrdy: master clock ready interrupt mask pckrdyx: programmable clock ready x interrupt mask 0 = the corresponding interrupt is enabled. 1 = the corresponding interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs
201 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27. debug unit (dbgu) 27.1 overview the debug unit provides a single entry point from the processor for access to all the debug capabilities of atmel?s arm-based systems. the debug unit features a two-pin uart that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communica- tions. moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. the debug unit also makes the debug communication channel (dcc) signals provided by the in-circuit emulator of the arm processor visible to the software. these signals indicate the sta- tus of the dcc read and write regi sters and generate an interrupt to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of the device and its revision. these registers inform as to the sizes and types of the on-chip memori es, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability that enables the software to decide whether to prevent access to the system via the in-circuit emulator. this permits protection of the code, stored in rom.
202 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.2 block diagram figure 27-1. debug unit functional block diagram figure 27-2. debug unit application example peripheral dma controller baud rate generator dcc handler ice access handler transmit receive chip id interrupt control peripheral bridge parallel input/ output dtxd drxd power management controller arm processor force_ntrst commrx commtx mck ntrst ice_nreset dbgu_irq apb debug unit table 27-1. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager
203 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.3 product dependencies 27.3.1 i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure t he corresponding pio controller to enable i/o lines operations of the debug unit. 27.3.2 power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the debug unit clock. usually, the peripheral identifier used for this purpose is 1. 27.3.3 interrupt source depending on product integration, the debug unit interrupt line is connected to one of the inter- rupt sources of the advanced interrupt controller. interrupt handling requires programming of the aic before configuring the de bug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 27-1 . this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.
204 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.4 uart operations the debug unit operates as a uart, (asynchronous mode only) and supports only 8-bit charac- ter handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not imple- mented. however, all the implemented features are compatible with those of a standard usart. 27.4.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, the baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allowable baud rate is master clock divided by (16 x 65536). figure 27-3. baud rate generator 27.4.2 receiver 27.4.2.1 receiver rese t, enable and disable after device reset, the debug unit receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writ ing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immedi ately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in it s reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. if rstrx is applied wh en data is being processed, this data is lost. baud rate mck 16 cd ---------------------- = mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock
205 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.4.2.2 start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a rece ived character by samplin g the drxd signal until it detects a valid start bit. a low level (space) on drxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical mid- point of each bit. it is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5 -bit periods) after t he falling edge of the st art bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 27-4. start bit detection figure 27-5. character reception 27.4.2.3 receiver ready when a complete character is received, it is transferred to the dbgu_rhr and the rxrdy sta- tus bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. figure 27-6. receiver ready sampling clock drxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy
206 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.4.2.4 receiver overrun if dbgu_rhr has not been read by the software (o r the peripheral data controller) since the last transfer, the rxrdy bit is still set and a ne w character is received, the ovre status bit in dbgu_sr is set. ovre is cleared when the soft ware writes the control register dbgu_cr with the bit rststa (reset status) at 1. figure 27-7. receiver overrun 27.4.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. figure 27-8. parity error 27.4.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same time the rxrdy bit is set. the bit frame remains high until the control register dbgu_cr is written with the bit rststa at 1. figure 27-9. receiver framing error d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop
207 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.4.3 transmitter 27.4.3.1 transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the co ntrol register dbgu_cr with the bit txen at 1. from this command, the transmitter waits for a ch aracter to be written in the transmit holding register dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 27.4.3.2 transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifte d out as shown on the following figure. the field pare in the mode register dbgu_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 27-10. character transmission 27.4.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status register dbgu_sr. the transmission starts when the pr ogrammer writes in the transmit holding regis- ter dbgu_thr, and after the written character is transferred from dbgu_thr to the shift register. the bit txrdy remains high until a se cond character is written in dbgu_thr. as soon as the first character is completed, the last character written in dbgu_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock
208 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 27-11. transmitter control 27.4.4 peripheral data controller both the receiver and the transmitter of the debug unit's uart are generally connected to a peripheral data controller (pdc) channel. the peripheral data controller channels are programmed via registers that are mapped within the debug unit user interface from the offset 0x100. the status bits are reported in the debug unit status register dbgu_sr and can generate an interrupt. the rxrdy bit triggers the pdc channel data transfer of the receiver. this results in a read of the data in dbgu_rhr. the txrdy bit triggers t he pdc channel data tran sfer of the transmit- ter. this results in a writ e of a data in dbgu_thr. 27.4.5 test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retr ansmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transm itter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitted characters to be received. dtxd and drxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the drxd pin level has no effect and th e dtxd line is held high , as in idle state. the remote loopback mode directly connects the drxd pin to the dtxd line. the transmitter and the receiver are disabled and have no effec t. this mode allows a bit-by-bit retransmission. dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop
209 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 27-12. test modes 27.4.6 debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug com- munication channel of the arm processor and are driven by the in-circuit emulator. the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions are used to read and write the debug communication channel: mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by t he debugger, are wired on the two highest bits of the status register dbgu_sr. these bits can generate an interrupt. this feature permits han- dling under interrupt a debug link between a debug monitor running on the target system and a debugger. receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
210 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.4.7 chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register) and dbgu_exid (extension id). both registers contain a hard-wired value that is read-only. the first register contains the following fields: ext - shows the use of the extension identifier register nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size arch - identifies the set of embedded peripheral sramsiz - indicates the size of the embedded sram eproc - indicates the embedded arm processor version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. 27.4.8 ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via the register force ntrst (dbgu_fnr), that allows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents any activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible.
211 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5 debug unit user interface table 27-2. debug unit memory map offset register name access reset value 0x0000 control register dbgu_cr write-only ? 0x0004 mode register dbgu_mr read/write 0x0 0x0008 interrupt enable register dbgu_ier write-only ? 0x000c interrupt disable register dbgu_idr write-only ? 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only ? 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only ? 0x0020 baud rate generator register dbgu_brgr read/write 0x0 0x0024 - 0x003c reserved ? ? ? 0x0040 chip id register dbgu_cidr read-only ? 0x0044 chip id extension register dbgu_exid read-only ? 0x0048 force ntrst register dbgu_fnr read/write 0x0 0x004c - 0x00fc reserved ? ? ? 0x0100 - 0x0124 pdc area ? ? ?
212 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.1 debug unit control register name: dbgu_cr access type: write-only rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a ch aracter is being received, the reception is aborted. rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processe d and rstrx is not set, the character is completed before the receiver is stopped. txen: transmitter enable 0 = no effect. 1 = the transmitter is ena bled if txdis is 0. txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is bei ng processed and a character has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
213 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.2 debug unit mode register name: dbgu_mr access type: read/write par: parity type chmode: channel mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chmode ?? pa r ? 76543210 ???????? pa r parity type 0 0 0 even parity 0 0 1 odd parity 0 1 0 space: parity forced to 0 0 1 1 mark: parity forced to 1 1 x x no parity chmode mode description 00normal mode 0 1 automatic echo 1 0 local loopback 1 1 remote loopback
214 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.3 debug unit interrupt enable register name: dbgu_ier access type: write-only rxrdy: enable rxrdy interrupt txrdy: enable txrdy interrupt endrx: enable end of receive transfer interrupt endtx: enable end of transmit interrupt ovre: enable overrun error interrupt frame: enable framing error interrupt pare: enable parity error interrupt txempty: enable txempty interrupt txbufe: enable buffer empty interrupt rxbuff: enable buffer full interrupt commtx: enable commtx (from arm) interrupt commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
215 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.4 debug unit interrupt disable register name: dbgu_idr access type: write-only rxrdy: disable rxrdy interrupt txrdy: disable txrdy interrupt endrx: disable end of receive transfer interrupt endtx: disable end of transmit interrupt ovre: disable overrun error interrupt frame: disable framing error interrupt pare: disable parity error interrupt txempty: disable txempty interrupt txbufe: disable buffer empty interrupt rxbuff: disable buffer full interrupt commtx: disable commtx (from arm) interrupt commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
216 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.5 debug unit interrupt mask register name: dbgu_imr access type: read-only rxrdy: mask rxrdy interrupt txrdy: disable txrdy interrupt endrx: mask end of receive transfer interrupt endtx: mask end of transmit interrupt ovre: mask overrun error interrupt frame: mask framing error interrupt pare: mask parity error interrupt txempty: mask txempty interrupt txbufe: mask txbufe interrupt rxbuff: mask rxbuff interrupt commtx: mask commtx interrupt commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
217 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.6 debug unit status register name: dbgu_sr access type: read-only rxrdy: receiver ready 0 = no character has been received since the last re ad of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to dbgu_rhr and not yet read. txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_thr not yet transferred to the shift register. endrx: end of receiver transfer 0 = the end of transfer signal from the receiver peripheral data controller channel is inactive. 1 = the end of transfer signal from the receiver peripheral data controller channel is active. endtx: end of transmitter transfer 0 = the end of transfer signal from the transmitter peripheral data controller channel is inactive. 1 = the end of transfer signal from the transmitter peripheral data controller channel is active. ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there ar e no characters being processed by the transmitter. txbufe: transmission buffer empty 0 = the buffer empty signal from the transmitter pdc channel is inactive. 1 = the buffer empty signal from the transmitter pdc channel is active. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
218 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary rxbuff: receive buffer full 0 = the buffer full signal from the receiver pdc channel is inactive. 1 = the buffer full signal from the receiver pdc channel is active. commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active.
219 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.7 debug unit receiver holding register name: dbgu_rhr access type: read-only rxchr: received character last received character if rxrdy is set. 27.5.8 debug unit transmit holding register name: dbgu_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr
220 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.9 debug unit baud ra te generator register name: dbgu_brgr access type: read/write cd: clock divisor 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd baud rate clock 0 disabled 1mck 2 to 65535 mck / (cd x 16)
221 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.10 debug unit chip id register name: dbgu_cidr access type: read-only version: version of the device eproc: embedded processor nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version eproc processor 0 0 1 arm946es 0 1 0 arm7tdmi 100arm920t 1 0 1 arm926ejs nvpsiz size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved
222 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary nvpsiz2 second nonvolatile program memory size sramsiz: internal sram size nvpsiz2 size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved sramsiz size 0000reserved 00011k bytes 00102k bytes 0011reserved 0100112k bytes 01014k bytes 011080k bytes 0111160k bytes 10008k bytes 100116k bytes 101032k bytes 101164k bytes 1100128k bytes 1101256k bytes 111096k bytes 1111512k bytes
223 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary arch: architecture identifier nvptyp: nonvolatile program memory type ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. arch architecture hex bin 0xf0 1111 0001 at75cxx series 0x40 0100 0000 at91x40 series 0x63 0110 0011 at91x63 series 0x55 0101 0101 at91x55 series 0x42 0100 0010 at91x42 series 0x92 1001 0010 at91x92 series 0x34 0011 0100 at91x34 series 0x60 0101 0000 at91sam7axx series 0x70 0111 0000 at91sam7sxx series 0x71 0111 0001 at91samxxx series 0x72 0111 0010 at91sam7sexx series 0x73 0111 0011 at91sam7lxx series 0x19 0001 1001 at91sam9xx series nvptyp memory 000rom 0 0 1 romless or on-chip flash 1 0 0 sram emulating rom 0 1 0 embedded flash memory 011 rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size
224 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 27.5.11 debug unit chip id extension register name: dbgu_exid access type: read-only exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. 27.5.12 debug unit force ntrst register name: dbgu_fnr access t ype: read/write fntrst: force ntrst 0 = ntrst of the arm processor?s tap contro ller is driven by the ice_nreset signal. 1 = ntrst of the arm processor?s tap controller is held low. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid 31 30 29 28 27 26 25 24 ??????? ? 23 22 21 20 19 18 17 16 ??????? ? 15 14 13 12 11 10 9 8 ??????? ? 7654321 0 ??????? fntrst
225 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28. parallel input/outp ut controller (pio) 28.1 overview the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: an input change interrupt enabling level change detection on any i/o line. a glitch filter providing rejection of pulses lower than one-half of clock cycle. multi-drive capability similar to an open drain i/o line. control of the the pull-up of the i/o line. input visibility and output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
226 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.2 block diagram figure 28-1. block diagram 28.3 application block diagram figure 28-2. application block diagram embedded peripheral embedded peripheral pio interrupt pio controller up to 32 pins pmc up to 32 peripheral ios up to 32 peripheral ios pio clock apb aic data, enable pin 31 pin 1 pin 0 data, enable on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
227 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.4 product dependencies 28.4.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio con- troller can control how the pin is driven by the product. 28.4.2 external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. 28.4.3 power management the power management controller controls the pio controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of t he features of the pio controller are available. note that the input change interrupt and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controller before any access to the input line information. 28.4.4 interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources 2 to 31. refer to the pio controller peripheral identifier in the produc t description to identify the interrupt sources dedicated to the pio controllers. the pio controller interrupt can be generated only if the pio controller clock is enabled.
228 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.5 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic asso- ciated to each i/o is represented in figure 28-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 28-3. i/o line control logic 1 0 1 0 1 0 glitch filter peripheral b input peripheral a input 1 0 pio_ifdr[0] pio_ifsr[0] pio_ifer[0] edge detector pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad 1 0 pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] 1 0 1 0 pio_bsr[0] pio_absr[0] pio_asr[0] peripheral b output enable peripheral a output enable peripheral b output peripheral a output pio_odr[0] pio_osr[0] pio_oer[0]
229 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.5.1 pull-up resistor control each i/o line is designed with an embedded pull-up resistor. the value of this resistor is about 10 k ? (see the product electrical characteristics for more details about this value). the pull-up resistor can be enabled or disabled by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull-up disable resi stor). writing in these registers results in setting or clearing the corresponding bit in pio_pusr (pull-up status register). reading a 1 in pio_pusr means the pull-up is disabled and reading a 0 means the pull-up is enabled. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0. 28.5.2 i/o line or peripheral function selection when a pin is multiplexed with one or two periph eral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the regis- ter pio_psr (pio status register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the co rresponding on-chip peripheral selected in the pio_absr (ab select status regist er). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the periph- eral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. 28.5.3 peripheral a or b selection the pio controller provides multiplexing of up to two peripheral functions on a single pin. the selection is performed by writing pio_asr (a select register) and pio_bsr (select b regis- ter). pio_absr (ab select status register) indicates which peripheral line is currently selected. for each pin, the corresponding bit at level 0 means peripheral a is selected whereas the corre- sponding bit at level 1 indicates that peripheral b is selected. note that multiplexing of peripheral lines a and b only affects the output line. the peripheral input lines are always connected to the pin input. after reset, pio_absr is 0, thus indicating that all the pio lines are configur ed on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_asr an d pio_bsr manages pio_absr regardless of th e configuration of the pin. however, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (pio_asr or pio_bsr) in addition to a write in pio_pdr. 28.5.4 output control when the i/0 line is assigned to a peripheral functi on, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b, depending on the value in pio_absr, determines whet her the pin is driven or not.
230 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary when the i/o line is controlled by the pio controller, the pin can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_odr (output disable register). the results of these write operations are detected in pio_osr (output status register). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (cle ar output data register). these write operations respectively set and clear pio_odsr (output data status register ), which represents the data driven on the i/o lines. writing in pio_oer and pio_odr manages pio_osr whether the pin is configured to be controlled by the pio controller or assigned to a peripheral function. this enables configura- tion of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. 28.5.5 synchronous data output controlling all paralle l busses using several pios requires two successive write operations in the pio_sodr and pio_codr registers. this may lead to unexpected transient values. the pio controller offers a direct control of pio outputs by single write access to pio_odsr (output data status register). only bits unmasked by pio_oswsr (output write status register) are written. the mask bits in the pio_owsr are se t by writing to pio_ower (output write enable register) and cleared by writing to pio_owdr (output write disable register). after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. 28.5.6 multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guar- antee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi-driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. 28.5.7 output line timings figure 28-4 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is valid only if the corresponding bit in pio_owsr is set. figure 28-4 also shows when the feedback in pio_pdsr is available.
231 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 28-4. output line timings 28.5.8 inputs the level on each i/o line can be read through pio_pdsr (pin data status register). this reg- ister indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 28.5.9 input glitch filtering optional input glitch filters are independently programmable on each i/o line. when the glitch fil- ter is enabled, a glitch with a duration of less than 1/2 master clock (mck) cycle is automatically rejected, while a pulse with a duration of 1 mast er clock cycle or more is accepted. for pulse durations between 1/2 master clock cycle and 1 master clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 master clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 master clock cycle. the filter introduces one master clock cycle latency if the pin level change occurs before a rising edge. however, this latency does not appear if the pin level chan ge occurs before a falling ed ge. this is illustrated in figure 28-5 . the glitch filters are controlled by the register set; pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and cl ears bits in pio_ifsr. this last register enables the glitch filt er on the i/o lines. when the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch filters require that the pio controller clock is enabled. 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
232 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 28-5. input glitch filter timing 28.5.10 input change interrupt the pio controller can be programmed to generate an interrupt when it detects an input change on an i/o line. the input change interrupt is cont rolled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change detection is possible only by comparing two successive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. configured as an input only, con- trolled by the pio controller or assigned to a peripheral function. when an input change is detected on an i/o line, the corresponding bit in pio_isr (interrupt status register) is set. if the corresponding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to gen- erate a single interrupt signal to the advanced interrupt controller. when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. figure 28-6. input change interrupt timings mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle mck pin level read pio_isr apb access pio_isr apb access
233 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.6 i/o lines programming example the programing example as shown in table 28-1 below is used to define the following configuration. 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor i/o lines 20 to 23 assigned to peripheral b functions, no pull-up resistor i/o line 24 to 27 assigned to peripheral a with input change interrupt and pull-up resistor table 28-1. programming example register value to be written pio_per 0x0000 ffff pio_pdr 0x0fff 0000 pio_oer 0x0000 00ff pio_odr 0x0fff ff00 pio_ifer 0x0000 0f00 pio_ifdr 0x0fff f0ff pio_sodr 0x0000 0000 pio_codr 0x0fff ffff pio_ier 0x0f00 0f00 pio_idr 0x00ff f0ff pio_mder 0x0000 000f pio_mddr 0x0fff fff0 pio_pudr 0x00f0 00f0 pio_puer 0x0f0f ff0f pio_asr 0x0f0f 0000 pio_bsr 0x00f0 0000 pio_ower 0x0000 000f pio_owdr 0x0fff fff0
234 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7 parallel input/output cont roller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio control- ler user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not mul- tiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 28-2. parallel input/output controller (pio) register mapping offset register name access reset value 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register (1) pio_psr read-only 0x0000 0000 0x000c reserved 0x0010 output enable register pio_oer write-only ? 0x0014 output disable register pio_odr write-only ? 0x0018 output status regist er pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter enab le register pio_ifer write-only ? 0x0024 glitch input filter disab le register pio_ifdr write-only ? 0x0028 glitch input filt er status register pio_ ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data r egister pio_sodr write-only ? 0x0034 clear output data r egister pio_codr write-only ? 0x0038 output data status register (2) pio_odsr read-only 0x0000 0000 0x003c pin data status register (3) pio_pdsr read-only 0x0040 interrupt enable register pio_ier write-only ? 0x0044 interrupt disable register pio_idr write-only ? 0x0048 interrupt mask regi ster pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only ? 0x0054 multi-driver disable register pio_mddr write-only ? 0x0058 multi-driver status re gister pio_mdsr read-only 0x00000000 0x005c reserved 0x0060 pull-up disable register pio_pudr write-only ? 0x0064 pull-up enable register pio_puer write-only ? 0x0068 pad pull-up status register pio_pusr read-only 0x00000000 0x006c reserved
235 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary notes: 1. reset value of pio_psr depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o lines. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. 5. only this set of registers clears the stat us by writing 1 in the first register and sets the status by writing 1 in the secon d register. 0x0070 peripheral a select register (5) pio_asr write-only ? 0x0074 peripheral b select register (5) pio_bsr write-only ? 0x0078 ab status register (5) pio_absr read-only 0x00000000 0x007c - 0x009c reserved 0x00a0 output write enable pio_ower write-only ? 0x00a4 output write disable pio_owdr write-only ? 0x00a8 output write status register pio_owsr read-only 0x00000000 0x00ac - 0x00fc reserved table 28-2. parallel input/output controller (pio) register mapping (continued) offset register name access reset value
236 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.1 pio controller pio enable register name: pio_per access type: write-only p0-p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). 28.7.2 pio controller pio disable register name: pio_pdr access type: write-only p0-p31: pio disable 0 = no effect. 1 = disables the pio from controllin g the corresponding pin (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
237 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.3 pio controller pio status register name: pio_psr access type: read-only p0-p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). 28.7.4 pio controller output enable register name: pio_oer access type: write-only p0-p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
238 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.5 pio controller output disable register name: pio_odr access type: write-only p0-p31: output disable 0 = no effect. 1 = disables the output on the i/o line. 28.7.6 pio controller output status register name: pio_osr access type: read-only p0-p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
239 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.7 pio controller input filter enable register name: pio_ifer access type: write-only p0-p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. 28.7.8 pio controller input filter disable register name: pio_ifdr access type: write-only p0-p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
240 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.9 pio controller input filter status register name: pio_ifsr access type: read-only p0-p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. 28.7.10 pio controller set output data register name: pio_sodr access type: write-only p0-p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
241 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.11 pio controller clear output data register name: pio_codr access type: write-only p0-p31: set output data 0 = no effect. 1 = clears the data to be driven on the i/o line. 28.7.12 pio controller output data status register name: pio_odsr access type: read-only or read/write p0-p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
242 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.13 pio controller pin data status register name: pio_pdsr access type: read-only p0-p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. 28.7.14 pio controller interrupt enable register name: pio_ier access type: write-only p0-p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
243 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.15 pio controller interrupt disable register name: pio_idr access type: write-only p0-p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. 28.7.16 pio controller interrupt mask register name: pio_imr access type: read-only p0-p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
244 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.17 pio controller interrupt status register name: pio_isr access type: read-only p0-p31: input change interrupt status 0 = no input change has been detected on the i/o line since pio_isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since pio_isr was last read or since reset. 28.7.18 pio multi-driver enable register name: pio_mder access type: write-only p0-p31: multi drive enable. 0 = no effect. 1 = enables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
245 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.19 pio multi-driver disable register name: pio_mddr access type: write-only p0-p31: multi drive disable. 0 = no effect. 1 = disables multi drive on the i/o line. 28.7.20 pio multi-driver status register name: pio_mdsr access type: read-only p0-p31: multi drive status. 0 = the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1 = the multi drive is enabled on the i/o lin e. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
246 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.21 pio pull up disable register name: pio_pudr access type: write-only p0-p31: pull up disable. 0 = no effect. 1 = disables the pull up resistor on the i/o line. 28.7.22 pio pull up enable register name: pio_puer access type: write-only p0-p31: pull up enable. 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
247 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.23 pio pull up status register name: pio_pusr access type: read-only p0-p31: pull up status. 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. 28.7.24 pio peripheral a select register name: pio_asr access type: write-only p0-p31: peripheral a select. 0 = no effect. 1 = assigns the i/o line to the peripheral a function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
248 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.25 pio peripheral b select register name: pio_bsr access type: write-only p0-p31: peripheral b select. 0 = no effect. 1 = assigns the i/o line to the peripheral b function. 28.7.26 pio peripheral a b status register name: pio_absr access type: read-only p0-p31: peripheral a b status. 0 = the i/o line is assigned to the peripheral a. 1 = the i/o line is assigned to the peripheral b. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
249 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.27 pio output write enable register name: pio_ower access type: write-only p0-p31: output write enable. 0 = no effect. 1 = enables writing pio_odsr for the i/o line. 28.7.28 pio output write disable register name: pio_owdr access type: write-only p0-p31: output write disable. 0 = no effect. 1 = disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
250 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 28.7.29 pio output write status register name: pio_owsr access type: read-only p0-p31: output write status. 0 = writing pio_odsr does not affect the i/o line. 1 = writing pio_odsr affects the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
251 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29. serial peripheral interface (spi) 29.1 overview the serial peripheral interface (spi) circuit is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. howeve r, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. slave select (nss): this control line allows slaves to be turned on and off by hardware.
252 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.2 block diagram figure 29-1. block diagram note: 1. n = 32 29.3 application block diagram figure 29-2. application block diagram: single master/multiple slave implementation spi interface interrupt control pio pdc pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 div npcs3 apb mck n (1) spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
253 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.4 signal description 29.5 product dependencies 29.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 29.5.2 power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first configure the pmc to enable the spi clock. 29.5.3 interrupt the spi interface has an interrupt line connected to the advanced interrupt controller (aic). handling the spi interrupt requires programming the aic before configuring the spi. table 29-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input
254 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.6 functional description 29.6.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the re ceiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. 29.6.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine th e edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 29-2 shows the four modes and corresponding parameter settings. figure 29-3 and figure 29-4 show examples of data transfers. table 29-2. spi bus protocol mode spi mode cpol ncpha 001 100 211 310
255 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 29-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 29-4. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
256 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.6.3 master mode operations when configured in master mode, the spi operates on the clock generated by the internal pro- grammable baud rate generator. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the trans mit data register and the receive data regis- ter, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (trans- mit data register). the written data is immediat ely transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. no transfer is started when writ ing into the spi_tdr if the pcs field does not select a slave. the pcs field is set by writing the spi_tdr in variable mode, or the spi_mr in fixed mode, depend- ing on the value of pcs field. if new data is written in spi_tdr during the transfe r, it stays in it until the current transfer is completed. then, the received data is transferred from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in t he shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is written in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit pdc channel. the end of transfer is indicated by the txempty flag in the spi_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift register in spi_rdr is indicated by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, no data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. figure 29-5 on page 257 shows a block diagram of the spi when operating in master mode. fig- ure 29-6 on page 258 shows a flow chart describing how transfers are handled.
257 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.6.3.1 master mode block diagram figure 29-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits 0 1 fdiv mck mck/n baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
258 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.6.3.2 master mode flow diagram figure 29-6. master mode flow diagram s spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
259 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.6.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck) or the master clock divided by 32, by a value between 2 and 255. the selection between master clock or master clock divided by n is done by the fdiv value set in the mode register this allows a maximum operating baud rate at up to master clock/2 and a minimum operating baud rate of mck divided by 255*32. programming the scbr field at 0 is forbidden. tri ggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 29.6.3.4 transfer delays figure 29-7 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: the delay between chip selects, programmable only once for all the ch ip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 29-7. programmable delays 29.6.3.5 peripheral selection the serial peripherals are selected through the as sertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. the peripheral selection can be performed in two different ways: dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
260 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary fixed peripheral select: spi exchanges data with only one peripheral variable peripheral select: data can be exchanged with more than one peripheral fixed peripheral select is activated by writing the ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs fields of the chip select registers have no effect. variable peripheral select is ac tivated by setting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the fixed peripheral selection allows buffer transfers with a single peripheral. using the pdc is an optimal means, as the size of the data transfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without repro- gramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is desti ned to. using the pdc in th is mode requires 32-bit wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, how- ever the spi still controls the number of bits (8 to16) to be transferred through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of mem- ory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 29.6.3.6 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with an external l ogic. this can be enabled by writing the pcs- dec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e. driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered chip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 29.6.3.7 peripheral deselection when operating normally, as soon as the transfer of the last data written in spi_tdr is com- pleted, the npcs lines all rise. this might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers.
261 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary to facilitate interfacing with such devices, the chip select regi ster can be programmed with the csaat bit (chip select active after transfer) at 1. this allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. figure 29-8 shows different peripheral deselection cases and the effect of the csaat bit. figure 29-8. peripheral deselection 29.6.3.8 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss signal. as this pin is generally configured in open- drain, it is important that a pull up resistor is connected on the npcs0 line, so that a high level is guaranteed and no spurious mode fault is detected. when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is automatically disabl ed until re-enabled by writing t he spien bit in the spi_cr (con- trol register) at 1. by default, the mode fault detection circuitr y is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 dlybct aa csaat = 1 a
262 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.6.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respectively by the ncpha and cpol bits of the spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if rdrf is already high wh en the data is transf erred, the overrun bit rises and the data transfer to spi_rdr is aborted. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (spi_tdr), the la st data received is transferred. if no data has been received since the last reset, all bits are transmitted low, as the shift regis- ter resets at 0. when a first data is written in sp i_tdr, it is transferred immediat ely in the shift register and the tdre bit rises. if new data is wri tten, it remains in spi_tdr until a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. w hen the transfer occurs, the last data written in spi_tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 29-9 shows a block diagram of the spi when operating in slave mode. figure 29-9. slave mode functional block diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits fload spien spidis miso
263 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7 serial peripheral inte rface (spi) user interface table 29-3. serial peripheral interface (spi) register mapping offset register register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read/write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read/write 0x0 0x34 chip select register 1 spi_csr1 read/write 0x0 0x38 chip select register 2 spi_csr2 read/write 0x0 0x3c chip select register 3 spi_csr3 read/write 0x0 0x004c - 0x00fc reserved ? ? ? 0x100 - 0x124 reserved for the pdc
264 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.1 spi control register name: spi_cr access type: write-only spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. spidis: spi disable 0 = no effect. 1 = disables the spi. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been tr ansferred. when c saat is set, this allows to close the communication with the current serial periph eral by raising the correspondi ng npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? ? ? spidis spien
265 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.2 spi mode register name: spi_mr access type: read/write mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 16 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 15. fdiv: clock selection 0 = the spi operates at mck. 1 = the spi operates at mck/n. modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled. llb controls the local loopback on the data serializer for testing in master mode only. pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? ? modfdis fdiv pcsdec ps mstr
266 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. dlybcs: delay between chip selects this field defines the delay from npcs inactive to the ac tivation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or equal to six, six mck periods (or 6*n mck period s if fdiv is set) will be inserted by default. otherwise, the following equat ion determines the delay: if fdiv is 0: if fdiv is 1: delay between chip selects dlybcs mck ---------------------- - = delay between chip selects dlybcs n mck ---------------------------------- =
267 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.3 spi receive data register name: spi_rdr access type: read-only rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd
268 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.4 spi transmit data register name: spi_tdr access type: write-only td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been tr ansferred. when c saat is set, this allows to close the communication with the current serial periph eral by raising the correspondi ng npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td
269 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.5 spi status register name: spi_sr access type: read-only rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_r dr is loaded at least twice from the serializer since the last read of the spi_rdr. endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in spi_rcr or spi_rncr. 1 = the receive counter re gister has reached 0 since the last write in spi_rcr or spi_rncr. endtx: end of tx buffer 0 = the transmit counter re gister has not reached 0 since the last write in spi_tcr or spi_tncr. 1 = the transmit counter re gister has reached 0 since the last write in spi_tcr or spi_tncr. rxbuff: rx buffer full 0 = spi_rcr or spi_rncr has a value other than 0. 1 = both spi_rcr and spi_rncr has a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
270 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary txbufe: tx buffer empty 0 = spi_tcr or spi_tncr has a value other than 0. 1 = both spi_tcr and spi_tncr has a value of 0. nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. txempty: transmission registers empty 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled.
271 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.6 spi interrupt enable register name: spi_ier access type: write-only rdrf: receive data register full interrupt enable tdre: spi transmit data regi ster empty interrupt enable modf: mode fault error interrupt enable ovres: overrun error interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable txempty: transmission registers empty enable nssr: nss rising interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
272 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.7 spi interrupt disable register name: spi_idr access type: write-only rdrf: receive data register full interrupt disable tdre: spi transmit data register empty interrupt disable modf: mode fault error interrupt disable ovres: overrun error interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable txempty: transmission registers empty disable nssr: nss rising interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
273 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.8 spi interrupt mask register name: spi_imr access type: read-only rdrf: receive data register full interrupt mask tdre: spi transmit data register empty interrupt mask modf: mode fault error interrupt mask ovres: overrun error interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask txempty: transmission registers empty mask nssr: nss rising interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
274 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 29.7.9 spi chip select register name: spi_csr0... spi_csr3 access type: read/write cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to c hange and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/da ta relationship between master and slave devices. csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is requested on a different chip select. bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat ? ncpha cpol bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
275 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: if fdiv is 0: if fdiv is 1: note: n = 32 programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can le ad to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: if fdiv is 0: if fdiv is 1: note: n = 32 dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transf ers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equat ion determines the delay: spck baudrate mck scbr -------------- - = spck baudrate mck nscbr () ------------------------------- = delay before spck dlybs mck ------------------ - = delay before spck ndlybs mck ----------------------------- - =
276 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary if fdiv is 0: if fdiv is 1: note: n = 32 delay between consecutive transfers 32 dlybct mck ------------------------------------- scbr 2 mck ---------------- - + = d elay between consecutive transfers 32 n dlybct mck ------------------------------------------------ - nscbr 2 mck -------------------------- + =
277 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30. two-wire interface (twi) 30.1 overview the two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-ori- ented transfer format. it can be used with any atme l two-wire bus serial eeprom. the twi is programmable as a master with sequential or single-byte access. a configurable baud rate gen- erator permits the output data rate to be adapted to a wide range of core clock frequencies. 30.2 block diagram figure 30-1. block diagram 30.3 application block diagram figure 30-2. application block diagram apb bridge pmc mck two-wire interface pio aic twi interrupt twck twd host with twi interface twd twck at24lc16 u1 at24lc16 u2 lcd controller u3 slave 1 slave 2 slave 3 rr vdd
278 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.4 product dependencies 30.4.1 i/o lines description both twd and twck are bidirectional lines, connect ed to a positive supply voltage via a current source or pull-up resistor (see figure 30-2 on page 277 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-and function. twd and twck pins may be multiplexed with pi o lines. to enable the twi, the programmer must perform the following steps: program the pio controller to: ? dedicate twd and twck as peripheral lines. ? define twd and twck as open-drain. 30.4.2 power management enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. 30.4.3 interrupt the twi interface has an interrupt line connected to the advanced interrupt controller (aic). in order to handle interrupts, the aic must be programmed before configuring the twi. table 30-1. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output
279 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.5 functional description 30.5.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 30-4 ). each transfer begins with a start condition and terminates with a stop condition (see figure 30-3 ). a high-to-low transition on the twd line while twck is high defines the start condition. a low-to-high transition on the twd line while twck is high defines a stop condition. figure 30-3. start and stop conditions figure 30-4. transfer format 30.5.2 modes of operation the twi has two modes of operation: master transmitter mode master receiver mode the twi control register (twi_cr) allows configuration of the interface in master mode. in this mode, it generates the clock according to the value programmed in the clock waveform gener- ator register (twi_cwgr). this register defines the twck signal completely, enabling the interface to be adapted to a wide range of clocks. 30.5.3 transmitting data after the master initiates a start condition, it sends a 7-bit slave address, configured in the mas- ter mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction (write or read). if this bit is 0, it indicates a write operation (transmit operation). if the bit is 1, it indica tes a request for data read (receive operation). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse, the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master po lls the data line during this clock pulse and twd twck start stop twd twck start address r/w ack data ack data ack stop
280 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary sets the nak bit in the status register if the slave does not acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). after writing in the transmit-holding register (twi_thr), setting the start bit in the control register starts the transmission. the data is shifted in the internal shifter and when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr (see figure 30- 6 below). the master generates a stop condition to end the transfer. the read sequence begins by setting the start bit. when the rxrdy bit is set in the status register, a character has been received in the receive-holding register (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. the twi interface performs various transfer formats (7-bit slave address, 10-bit slave address). the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, iadrsz must be set to 0. for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). figure 30-5. master write with one, two or three bytes internal address and one data byte figure 30-6. master write with one byte internal address and multiple data bytes figure 30-7. master read with one, two or three bytes internal address and one data byte s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data ap s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd a iadr(7:0) a data a s dadr w data a p data a txcomp txrdy write thr write thr write thr write thr twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p s dadr r a s dadr r a data n p s dadr r a data n p twd twd twd three bytes internal address two bytes internal address one byte internal address
281 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 30-8. master read with one byte internal address and multiple data bytes s = start p = stop w = write r = read a = acknowledge n = not acknowledge dadr = device address iadr = internal address figure 30-9 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 30-9. internal address usage 30.5.4 read/write flowcharts the following flowcharts shown in figure 30-10 on page 282 and in figure 30-11 on page 283 give examples for read and write operations in master mode. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. a iadr(7:0) a s dadr w s dadr r a data a data n p txcomp write start bit rxrdy write stop bit read rhr read rhr twd s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
282 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 30-10. twi write in master mode set twi clock: twi_cwgr = clock set the control register: - master enable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send start the transfer twi_cr = start stop the transfer twi_cr = stop read status register txrdy = 0? data to send? read status register txcomp = 0? end start set theinternal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s
283 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 30-11. twi read in master mode set twi clock: twi_cwgr = clock set the control register: - master enable - slave disable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit read ==> bit mread = 0 internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 0? data to read? read status register txcomp = 0? end start set the internal address twi_iadr = address ye s ye s ye s ye s
284 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6 two-wire interface (t wi) user interface table 30-2. two-wire interface (twi) register mapping offset register name access reset value 0x0000 control register twi_cr write-only n/a 0x0004 master mode register twi_mmr read/write 0x0000 0x0008 reserved ? ? ? 0x000c internal address register twi_iadr read/write 0x0000 0x0010 clock waveform generator register twi_cwgr read/write 0x0000 0x0020 status register twi_sr read-only 0x0008 0x0024 interrupt enable register twi_ier write-only n/a 0x0028 interrupt disable register twi_idr write-only n/a 0x002c interrupt mask register twi_imr read-only 0x0000 0x0030 receive holding register twi_rhr read-only 0x0000 0x0034 transmit holding register twi_thr read/write 0x0000 0x0038-0x00fc reserved ? ? ?
285 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.1 twi control register register name :twi_cr access type: write-only start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read or write mode. in single data byte master read or write, the start and stop must both be set. in multiple data bytes master read or write, the stop must be set before ack/nack bit transmission. in master read mode, if a nack bit is received, the stop is automatically performed. in multiple data write operation, when both thr and shift register are empty, a stop condition is automatically sent. msen: twi master transfer enabled 0 = no effect. 1 = if msdis = 0, the master data transfer is enabled. msdis: twi master transfer disabled 0 = no effect. 1 = the master data transfer is disabled, all pending data is tr ansmitted. the shifter and holding characters (if they contain data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. swrst: software reset 0 = no effect. 1 = equivalent to a system reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? msdis msen stop start
286 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.2 twi master mode register register name :twi_mmr address type : read/write iadrsz: internal device address size mread: master read direction 0 = master write direction. 1 = master read direction. dadr: device address the device address is used in master mode to access slave devices in read or write mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ???mread?? iadrsz 76543210 ???????? iadrsz[9:8] 0 0 no internal device address (byte command protocol) 0 1 one-byte internal device address 1 0 two-byte internal device address 1 1 three-byte internal device address
287 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.3 twi internal address register register name :twi_iadr access type : read/write iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. ? low significant byte address in 10-bit mode addresses. 30.6.4 twi clock waveform generator register register name : twi_cwgr access type : read/write cldiv: clock low divider the scl low period is defined as follows: chdiv: clock high divider the scl high period is defined as follows: ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 3 ) + t mck = t high chdiv ( 2 ckdiv () 3 ) + t mck =
288 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.5 twi status register register name :twi_sr access type : read-only txcomp: transmission completed 0 = in master, during the length of the current frame. in slave, from start received to stop received. 1 = when both holding and shift registers are empty and stop condition has been sent (in master) or when msen is set (enable twi). rxrdy: receive hold ing register ready 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. txrdy: transmit holding register ready 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as data byte is transferred from twi_thr to internal shifter or if a nack error is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). ovre: overrun error 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. unre: underrun error 0 = no underrun error 1 = no valid data in twi_thr (txrdy set) while trying to load the data shifter. this action automatically generated a stop bit in master mode. reset by read in twi_sr when txcomp is set. nack: not acknowledged 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the slave compon ent. set at the same time as txcomp. reset after read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
289 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.6 twi interrupt enable register register name :twi_ier access type: write-only txcomp: transmission completed rxrdy: receive hold ing register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
290 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.7 twi interrupt disable register register name :twi_idr access type: write-only txcomp: transmission completed rxrdy: receive hold ing register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
291 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.8 twi interrupt mask register register name :twi_imr access type : read-only txcomp: transmission completed rxrdy: receive hold ing register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
292 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6.9 twi receive holding register register name : twi_rhr access type : read-only rxdata: master or slave receive holding data 30.6.10 twi transmit holding register register name :twi_thr access type: read/write txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
293 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31. universal synchronous asynchrono us receiver transmitter (usart) 31.1 overview the universal synchronous asynchronous rece iver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely program- mable (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time- out enables handling variable-length fr ames and the trans mitter timeguard facilitates commu- nications with slow remote devices. multidrop communications are also supported through address bit handling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485 buses, with iso7816 t = 0 or t = 1 smart card slots, infrared transceivers and connection to modem ports. the hardware handshaking feature enables an out-of-band flow control by automatic manage- ment of the pins rts and cts. the usart supports the connection to the peripheral dma controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor.
294 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.2 block diagram figure 31-1. usart block diagram peripheral dma controller channel channel aic receiver usart interrupt rxd txd sck usart pio controller cts rts dtr dsr dcd ri transmitter modem signals control baud rate generator user interface pmc mck slck div mck/div apb
295 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.3 application block diagram figure 31-2. application block diagram 31.4 i/o lines description table 31-1. i/o line description name description type active level sck serial clock i/o txd transmit serial data i/o rxd receive serial data input ri ring indicator input low dsr data set ready input low dcd data carrier detect input low dtr data terminal ready output low cts clear to send input low rts request to send output low smart card slot usart rs232 drivers modem rs485 drivers differential bus irda transceivers modem driver field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp pstn
296 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.5 product dependencies 31.5.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. all the pins of the modems may or may not be implemented on the usart within a product. frequently, only the usart1 is fully equipped with all the modem signals. for the other usarts of the product not equipped with the co rresponding pin, the associated control bits and statuses have no effect on the behavior of the usart. 31.5.2 power management the usart is not continuously clocked. the programmer must first enable the usart clock in the power management controller (pmc) before using the usart. however, if the applica- tion does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its op erations where it left off. configuring the usart does not require the usart clock to be enabled. 31.5.3 interrupt the usart interrupt line is connected on one of the internal sources of the advanced inter- rupt controller. using the usart interrupt requires the aic to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode.
297 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.6 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multidrop serial communication high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multidrop serial communication rs485 with driver control signal iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit infrared irda modulation and demodulation test modes ? remote loopback, local loopback, automatic echo 31.6.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: the master clock mck a division of the master clock, the divider being product dependent, but generally set to 8 the external clock, available on the sck pin the baud rate generator is based upon a 16-bit di vider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed at 0, the baud rate generator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive.
298 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck. figure 31-3. baud rate generator 31.6.1.1 baud rate in asynchronous mode if the usart is programmed to operate in asynchronous mode, the selected clock is first divided by cd, which is field programmed in th e baud rate generator register (us_brgr). the resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest pos- sible clock and that over is programmed at 1. baud rate calculation example table 31-2 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- = table 31-2. baud rate exam ple (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00%
299 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. 31.6.1.2 fractional baud rate in asynchronous mode the baud rate generator previously defined is s ubject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate changes by a fraction of the reference source clock. this fractional part is programmed with the fp field in the baud rate generator regis- ter (us_brgr). if fp is not 0, the fractional par t is activated. the resolution is one eighth of the clock divider. this feature is only availabl e when using usart functional mode. the frac- tional baud rate is calculated using the following formula: 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% 70 000 000 38 400 113.93 114 38 377.19 0.06% table 31-2. baud rate example (over = 0) (continued) source clock expected baud rate calculation result cd actual baud rate error b audrate mck cd 1 6 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? = baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? ---------------------------------------------------------------- - =
300 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the modified architecture is presented below: figure 31-4. fractional baud rate generator 31.6.1.3 baud rate in synchronous mode if the usart is programmed to operate in sync hronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. when either the external clock sck or the internal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is sele cted, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. 31.6.1.4 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: where: b is the bit rate di is the bit-rate adjustment factor fi is the clock frequency division factor f is the iso7816 clock frequency (hz) mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi glitch-free logic modulus control fp fp baudrate selectedclock cd ------------------------------------- - = b di fi ----- - f =
301 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary di is a binary value encoded on a 4-bit field, named di, as represented in table 31-3 . fi is a binary value encoded on a 4-bi t field, named fi, as represented in table 31-4 . table 31-5 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, the clock selected by the usclks field in the mode register (us_mr) is first divided by the va lue programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value programmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not sup- ported and the user must program the fi_di_rati o field to a value as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 31-5 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. table 31-3. binary and decimal values for d di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal) 1 2 4 8 16 32 12 20 table 31-4. binary and decimal values for f fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 31-5. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
302 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-5. elementary time unit (etu) 31.6.2 receiver and transmitter control after reset, the receiver is disabled. the user mu st enable the receiver by setting the rxen bit in the control register (us_cr). however, th e receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is di sabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rs ttx respectively, in the control register (us_cr). the reset commands have the same effect as a hardware reset on the correspond- ing logic. regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. the user can also independently disable the rece iver or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operat ing, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a timeguard is programmed, it is handled normally. 31.6.3 synchronous and asynchronous modes 31.6.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode9 bit in the mode regis- ter (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par fiel d in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf fi eld in us_mr configures which data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less significant bit is sent first. the number of stop bits is selected by the nbstop field in us_mr. the 1.5 stop bit is sup- ported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
303 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-6. character transmit the characters are sent by writing in the tr ansmit holding register (us_thr). the transmit- ter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empt y and txempty, which indicates that all the characters written in us_thr have been proces sed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy raises. both txrdy and txempty bits are low since the transmitter is disabled. writing a character in us_thr while txrdy is active has no ef fect and the written character is lost. figure 31-7. transmitter status 31.6.3.2 manchester encoder when the manchester encoder is in use, characters transmitted through the usart are encoded based on biphase manchester ii format. to enable this mode, set the man field in the us_mr register to 1. depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-t o-one. thus, a transition always occurs at the midpoint of each bit time. it consumes more bandwidth than the original nrz signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. an example of m anchester encoded sequence is: the byte 0xb1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. figure 31-8 illustrates this coding scheme. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
304 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-8. nrz to manchester encoding the manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. if the preamble length is set to 0, the preamble waveform is not generated prior to any character. the preamble pattern is chosen among the following sequences: all_one, all_zero, one_zero or zero_one, writing the field tx_pp in the us_man register, the field tx_pl is used to configure the preamble length. figure 31-9 illustrates and defines the valid patterns. to improve flexibility, the encoding scheme can be configured using the tx_mpol field in the us_man register. if the tx _mpol field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. if the tx_mpol field is set to one, a logic one is encoded with a one-to-zero transi- tion and a logic zero is encoded with a zero-to-one transition. figure 31-9. preamble patterns, default polarity assumed a start frame delimiter is to be configured using the onebit field in the us_mr register. it consists of a user-defined pattern that indicates the beginning of a valid data. figure 31-10 illustrates these patterns. if the start frame delimiter, also known as start bit, is one bit, (onebit at 1), a logic zero is manchester encoded and indicates that a new character is being sent serially on the line. if the start frame delimiter is a synchronization pattern also referred to as sync (onebit at 0), a sequence of 3 bit times is sent serially on the line to indicate the start nrz encoded data manchester encoded data 10110001 txd manchester encoded data txd sfd data 8 bit width "all_one" preamble manchester encoded data txd sfd data 8 bit width "all_zero" preamble manchester encoded data txd sfd data 8 bit width "zero_one" preamble manchester encoded data txd sfd data 8 bit width "one_zero" preamble
305 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary of a new character. the sync waveform is in itself an invalid manchester waveform as the tran- sition occurs at the middle of the second bit time. two distinct sync patterns are used: the command sync and the data sync. the command sync has a logic one level for one and a half bit times, then a transition to logic zero fo r the second one and a half bit times. if the sync field in the us_mr register is set to 1, the next character is a command. if it is set to 0, the next character is a data. when direct memory access is used, the sync field can be immedi- ately updated with a modified character located in memory. to enable this mode, var_sync field in us_mr register must be set to 1. in this case, the sync field in us_mr is bypassed and the sync configuration is held in the t xsynh in the us_thr register. the usart char- acter format is modified and includes sync information. figure 31-10. start frame delimiter drift compensation drift compensation is available only in 16x oversampling mode. an hardware recovery system allows a larger clock drift. to enable the hardware system, the bit in the usart_man register must be set. if the rxd edge is one 16x clock cy cle from the expected edge, this is consid- ered as normal jitter and no corrective actions is taken. if the rxd event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. if the rxd event is between 2 and 3 cloc k cycles after the expected edge, then the cur- rent period is lengthened by one clock cycle. th ese intervals are considered to be drift and so corrective actions are automatically taken. manchester encoded data txd sfd data one bit start frame delimiter preamble length is set to 0 manchester encoded data txd sfd data command sync start frame delimiter manchester encoded data txd sfd data data sync start frame delimiter
306 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-11. bit resynchronization 31.6.3.3 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bi ts are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on ea ch 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl, mo de9, msbf and par. the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchro- nization can also be accomplished when the transmitter is operating with one stop bit. figure 31-12 and figure 31-13 illustrate start dete ction and character reception when usart operates in asynchronous mode. rxd oversampling 16x clock sampling point expected edge tolerance synchro. jump sync jump synchro. error synchro. error
307 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-12. asynchronous start detection figure 31-13. asynchronous character reception 31.6.3.4 manchester decoder when the man field in us_mr register is set to 1, the manchester decoder is enabled. the decoder performs both preamble and start frame delimiter detection. one input line is dedi- cated to manchester encoded input data. an optional preamble sequence can be defined, its length is user-defined and totally indepen- dent of the emitter side. use rx_pl in us_man register to configure the length of the preamble sequence. if the length is set to 0, no preamble is detected and the function is dis- abled. in addition, the polarity of the input stream is programmable with rx_mpol field in us_man register. depending on the desired application the preamble pattern matching is to be defined via the rx_pp field in us_man. see figure 31-9 for available preamble patterns. unlike preamble, the start frame delimiter is shared between manchester encoder and decoder. so, if onebit field is set to 1, only a zero encoded manchester can be detected as a valid start frame delimiter. if onebit is set to 0, only a sync pattern is detected as a valid start frame delimiter. decoder operates by detecting transition on incoming stream. if rxd is sampled during one quarter of a bit time at zero, a start bit is detected. see figure 31-14 .. the sample pulse reject ion mechanism applies. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
308 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-14. asynchronous star t bit detection the receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. if a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. if the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.the minimum time threshold to esti mate the bit value is three quarters of a bit time. if a valid preamble (if used) fo llowed with a valid start frame delim iter is detected, the incoming stream is decoded into nrz data and passed to usart for processing. figure 31-15 illus- trates manchester pattern mismatch. when incoming data stream is passed to the usart, the receiver is also able to detect manchester co de violation. a code violation is a lack of tran- sition in the middle of a bit cell. in this case , mane flag in us_csr register is raised. it is cleared by writing the control register (u s_cr) with the rststa bit at 1. see figure 31-16 for an example of manchester error detection during data phase. figure 31-15. preamble pattern mismatch figure 31-16. manchester error flag manchester encoded data txd 1234 sampling clock (16 x) start detection manchester encoded data txd sfd data preamble length is set to 8 preamble mismatch invalid pattern preamble mismatch manchester coding error manchester encoded data txd sfd preamble length is set to 4 elementary character bit time manchester coding error detected sampling points preamble subpacket and start frame delimiter were successfully decoded entering usart character area
309 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary when the start frame delimiter is a sync pattern (onebit field at 0), both command and data delimiter are supported. if a valid sync is detect ed, the received characte r is written as rxchr field in the us_rhr register and the rxsyn h is updated. rxchr is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. this mechanism alleviates and simplifies the direct me mory access as the character contains its own sync field in the same register. the decoder does not perform pipelining of incoming data stream. thus when unipolar mode is enabled, it is highly recommended to assure consistency between start frame delimiter (or preamble) waveform and default active level. ex ample: when the line idles, the logic level is one; to synchronize and avoid confusion, a zero-to-one transition is mandatory. 31.6.3.5 radio interface: manchester encoded usart application this section describes low data rate rf tr ansmission systems and their integration with a manchester encoded usart. these systems are based on transmitter and receiver ics that support ask and fsk modulation schemes. the goal is to perform full duplex radio trans mission of characters using two different fre- quency carriers. see the configuration in figure 31-17 . figure 31-17. manchester encoded characters rf transmission the usart module is configured as a manches ter encoder/decoder. it is also highly recom- mended to use pio interface to access rf receiver configuration registers. looking at the downstream communication channel, manchester enc oded characters are serially sent to the rf emitter. this may also include a user defined preamble and a start frame delimiter. mostly, preamble is used in the rf receiver to distinguish between a valid data from a transmitter and signals due to noise. the manchester stream is then modulated. see figure 31-18 for an example of ask modulation scheme. when a l ogic one is sent to the ask modulator, the power amplifier, referred to as pa, is enabl ed and transmits an rf signal at downstream fre- quency. when a logic zero is transmitted, the rf signal is turned off. if the fsk modulator is activated, two different frequencies are used to transmit data. when a logic 1 is sent, the mod- lna vco rf filter demod control bi-dir line pa rf filter mod vco control manchester decoder manchester encoder usart receiver usart emitter ask/fsk upstream receiver ask/fsk downstream transmitter upstream emitter downstream receiver serial configuration interface fup frequency carrier fdown frequency carrier
310 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary ulator outputs an rf signal at frequency f0 and switches to f1 if the data sent is a 0. see figure 31-19 . from the receiver side, another carrier frequency is used. the rf receiver performs a bit check operation examining demodulated data stream. if a valid pattern is detected, the receiver switches to receiving mode. the dem odulated stream is sent to the manchester decoder. because of bit checking inside rf ic, th e data transferred to the microcontroller is reduced by a user-defined number of bits. the manchester preamble length is to be defined in accordance with the rf ic configuration. figure 31-18. ask modulator output figure 31-19. fsk modulator output 31.6.3.6 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a low level is detected, it is considered as a start. all data bits, the par- ity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a hi gh speed trans fer capability. configuration fields and bits are the same as in asynchronous mode. figure 31-20 illustrates a character rec eption in synchronous mode. manchester encoded data default polarity unipolar output txd ask modulator output uptstream frequency f0 nrz stream 10 0 1 manchester encoded data default polarity unipolar output txd fsk modulator output uptstream frequencies [f0, f0+offset] nrz stream 10 0 1
311 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-20. synchronous mode character reception 31.6.3.7 receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status regi ster (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into us_rhr and overwrites the previ ous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit at 1. figure 31-21. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr
312 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.6.3.8 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 313 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, a nd at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the samp led parity bit does not correspond. if the mark parity is used, the parity generator of the transmitte r drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0. if the space parity is used, the parity generator of the transmitter driv es the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 31-6 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. when the receiver detects a parity error, it sets the pare (parity error) bit in the channel sta- tus register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit at 1. figure 31-22 illustrates the parity bit st atus setting and clearing. table 31-6. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
313 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-22. parity error 31.6.3.9 multidrop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bi t set) when senda is written to us_cr. in this case, the next byte written to us_thr is transmitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity at 0. 31.6.3.10 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard reg- ister (us_ttgr). when this field is programmed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 31-23 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 during the timegua rd transmission if a character has been written in us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
314 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-23. timeguard operations table 31-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 31.6.3.11 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out register (us_rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains at 0. otherwise, the receiver loads a 16-bit counter with the value pro- grammed in to. this counter is decremented at each bit period and reloaded each time a new character is received. if the c ounter reaches 0, the timeout bit in the status register rises. the user can either: d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 31-7. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
315 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary obtain an interrupt when a time-out is detected after having received at least one character. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit at 1. obtain a periodic interrupt while no characte r is received. this is performed by writing us_cr with the retto (reload and start time-out) bit at 1. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. figure 31-24 shows the block diagram of the receiver time-out feature. figure 31-24. receiver time-out block diagram table 31-8 gives the maximum time-out period for some standard baud rates. table 31-8. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
316 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.6.3.12 framing error the receiver is capable of detecting framing er rors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bi t as soon as the framing error is detected. it is cleared by writing the control regist er (us_cr) with the rststa bit at 1. figure 31-25. framing error status 31.6.3.13 transmit break the user can request the transmitter to generate a break condition on the txd line. a break condition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until t he user requests the break condition to be removed. a break is transmitted by writing the control regi ster (us_cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the characte r is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with the both sttbrk and stpb rk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending, but not started, is ignored. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
317 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 31-26 illustrates the effect of both the start break (sttbrk) and stop break (stp- brk) commands on the txd line. figure 31-26. break transmission 31.6.3.14 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control re gister (us_cr) with the bit rststa at 1. an end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 31.6.3.15 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 31-27 . figure 31-27. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break usart txd cts remote device rxd txd rxd rts rts cts
318 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, exce pt that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires using the pdc channel for reception. the transmit- ter can handle hardware handshaking in any case. figure 31-28 shows how the receiver operates if ha rdware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) coming from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled, the rts falls, indicating to the remote device that it can start transmitting. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 31-28. receiver behavior when operating with hardware handshaking figure 31-29 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitter. if a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character hap- pens as soon as the pin cts falls. figure 31-29. transmitter behavior when operating with hardware handshaking 31.6.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protocol t = 0 and to the value 0x5 for protocol t = 1. 31.6.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clock provided to the remote device (see ?baud rate genera- tor? on page 297 ). the usart connects to a smart card as shown in figure 31-30 . the txd line becomes bidi- rectional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains dr iven by the output of the transmitter but only rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd
319 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary when the transmitter is active wh ile its input is directed to the input of the receiver. the usart is considered as the master of the communication as it generates the clock. figure 31-30. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmo de fields. msbf can be used to transmit lsb or msb first. the usart cannot operate concurrently in both receiver and transmitter modes as the com- munication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse trans mission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this format and the user has to perform an exclusive or on the data before writing it in the trans- mit holding register (us_thr) or after reading it in the receive hold ing register (us_rhr). 31.6.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 31-31 . if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 31-32 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous charac- ter in the receive holding register (us_rhr). it appropriately sets the pare bit in the status register (us_sr) so that the software can handle the error. smart card sck clk txd i/o usart
320 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-31. t = 0 protocol without parity error figure 31-32. t = 0 protocol with parity error receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. receive nack inhibit the usart can also be configur ed to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inac k bit is set in the status register (us_sr). the inack bit can be cleared by writing the control register (us_cr) with the rstnack bit at 1. moreover, if inack is set, the erroneous received character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each charac- ter can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. when the usart repetition number reaches m ax_iteration, the iterat ion bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit at 1. d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
321 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 31.6.4.3 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). 31.6.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 31-33 . the modulator and demodulator are compli- ant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting t he usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodula- tor filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 31-33. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter
322 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.6.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. ?0? is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 31-9 . figure 31-34 shows an example of character transmission. figure 31-34. irda modulation 31.6.5.2 irda baud rate table 31-10 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. table 31-9. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 31-10. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88
323 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.6.5.3 irda demodulator the demodulator is based on the irda receive filter comprised of an 8-bit down counter which is loaded with the value progra mmed in us_if. when a falling e dge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 31-35 illustrates the operations of the irda demodulator. figure 31-35. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 table 31-10. irda baud rate error (continued) peripheral clock baud rate cd baud rate error pulse time mck rxd receiver input pulse rejected 65432 6 1 driven low during 16 baud rate clock cycles 65432 0 pulse accepted counter value
324 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.6.6 rs485 mode the usart features the rs485 mode to enable line driver control. while operating in rs485 mode, the usart behaves as though in asynchronous or synchronous mode and configura- tion of all the parameters is possible. the differenc e is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typ- ical connection of the usart to a rs485 bus is shown in figure 31-36 . figure 31-36. typical connection to a rs485 bus the usart is set in rs485 mode by programming the usart_mode field in the mode reg- ister (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempty bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. figure 31-37 gives an example of the rts waveform during a character transmis- sion when the timeguard is enabled. figure 31-37. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
325 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.6.7 modem mode the usart features modem mode, which enables control of the signals: dtr (data terminal ready), dsr (data set ready), rts (request to send), cts (clear to send), dcd (data carrier detect) and ri (ring indicator). while operating in modem mode, the usart behaves as a dte (data terminal equipment) as it drives dtr and rts and can detect level change on dsr, dcd, cts and ri. setting the usart in modem mode is performe d by writing the usart_mode field in the mode register (us_mr) to the value 0x3. while operating in modem mode the usart behaves as though in asynchronous mode and all the parameter configurations are available. table 31-11 gives the correspondence of the usart signals with modem connection standards. the control of the rts and dtr output pins is performed by witting the control register (us_cr) with the rtsdis, rtsen, dtrdis and dt ren bits respectively at 1. the disable command forces the corresponding pin to its inactive level, i.e. high. the enable commands force the corresponding pin to its active level, i.e. low. the level changes are detected on the ri, dsr, dcd and cts pins. if an input change is detected, the riic, dsric, dcdic and ctsic bits in the channel status register (us_csr) are set respectively and can trigger an interr upt. the status is automatically cleared when us_csr is read. furthermore, the cts automa tically disables the transmitter when it is detected at its inactive state. if a character is being transmitted when the cts rises, the char- acter transmission is completed before the transmitter is actually disabled. 31.6.8 test modes the usart can be programmed to operate in three different test modes. the internal loop- back capability allows on-board diagnostics. in the loopback mode the usart interface pins are disconnected or not and reconfigured for loopback internally or externally. 31.6.8.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. table 31-11. circuit references usart pin v24 ccitt direction txd 2 103 from terminal to modem rts 4 105 from terminal to modem dtr 20 108.2 from terminal to modem rxd 3 104 from modem to terminal cts 5 106 from terminal to modem dsr 6 107 from terminal to modem dcd 8 109 from terminal to modem ri 22 125 from terminal to modem
326 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-38. normal mode configuration 31.6.8.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 31-39 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 31-39. automatic echo mode configuration 31.6.8.3 local loopback mode local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in figure 31-40 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 31-40. local loopback mode configuration 31.6.8.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 31- 41 . the transmitter and the receiver are disabled an d have no effect. this mode allows bit-by- bit retransmission. receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1
327 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 31-41. remote loopback mode configuration receiver transmitter rxd txd 1
328 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7 usart user interface table 31-12. usart memory map offset register name access reset state 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read/write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0x0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0x0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read/write 0x0 0x0024 receiver time-out register us_rtor read/write 0x0 0x0028 transmitter timeguard register us_ttgr read/write 0x0 0x2c - 0x3c reserved ? ? ? 0x0040 fi di ratio register us_fidi read/write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter register us_if read/write 0x0 0x0050 manchester encoder decoder register us_man read/write 0x0 0x5c - 0xfc reserved ? ? ? 0x100 - 0x128 reserved for pdc registers ? ? ?
329 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.1 usart control register name: us_cr access type: write-only rstrx: reset receiver 0: no effect. 1: resets the receiver. rsttx: reset transmitter 0: no effect. 1: resets the transmitter. rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. rxdis: receiver disable 0: no effect. 1: disables the receiver. txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. txdis: transmitter disable 0: no effect. 1: disables the transmitter. rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre and rxbrk in the us_csr. sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in us_thr and the transmit shi ft register have been trans- mitted. no effect if a break is already being transmitted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdisrtsendtrdisdtren 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
330 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. sttto: start time-out 0: no effect 1: starts waiting for a character before clocking the time-out counter. senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the us_thr is sent with the address bit set. rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no e ffect if the iso7816 is not enabled. rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. retto: rearm time-out 0: no effect 1: restart time-out dtren: data terminal ready enable 0: no effect. 1: drives the pin dtr at 0. dtrdis: data terminal ready disable 0: no effect. 1: drives the pin dtr to 1. rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1.
331 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.2 usart mode register name: us_mr access type: read/write usart_mode usclks: clock selection 31 30 29 28 27 26 25 24 onebit ? man filter ? max_iteration 23 22 21 20 19 18 17 16 ? var_sync dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode usart_mode mode of the usart 0000normal 0001rs485 0010hardware handshaking 0011modem 0100is07816 protocol: t = 0 0101reserved 0110is07816 protocol: t = 1 0111reserved 1000irda 11xxreserved usclks selected clock 00mck 01mck / div 10reserved 11sck
332 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary chrl: character length. sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. par: parity type nbstop: number of stop bits chmode: channel mode msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. mode9: 9-bit character length 0: chrl defines character length. chrl character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits par parity type 0 0 0 even parity 0 0 1 odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 1 0 x no parity 1 1 x multidrop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input.. 1 1 remote loopback. rxd pin is internally connected to the txd pin.
333 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 1: 9-bit character length. cklo: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity erro r occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value spec ified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is r eached, no additional nack is sent on the iso line. the flag iteration is asserted. var_sync: variable synchronization of command/data sync start frame delimiter 0: user defined configuration of command or data sync field depending on sync value. 1: the sync field is updated when a char acter is written into us_thr register. max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). man: manchester encoder/decoder enable 0: manchester encoder/decoder are disabled. 1: manchester encoder/decoder are enabled. onebit: start frame delimiter selector 0: start frame delimiter is command or data sync. 1: start frame delimiter is one bit.
334 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.3 usart interrupt enable register name: us_ier access type: write-only rxrdy: rxrdy interrupt enable txrdy: txrdy interrupt enable rxbrk: receiver break interrupt enable endrx: end of receive transfer interrupt enable endtx: end of transmit interrupt enable ovre: overrun error interrupt enable frame: framing error interrupt enable pare: parity error interrupt enable timeout: time-out interrupt enable txempty: txempty interrupt enable iteration: iteration interrupt enable txbufe: buffer empty interrupt enable rxbuff: buffer full interrupt enable nack: non acknowledge interrupt enable riic: ring indicator input change enable dsric: data set ready input change enable dcdic: data carrier detect input change interrupt enable ctsic: clear to send input change interrupt enable mane: manchester error interrupt enable 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? mane ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
335 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.4 usart interrupt disable register name: us_idr access type: write-only rxrdy: rxrdy interrupt disable txrdy: txrdy interrupt disable rxbrk: receiver bre ak interrupt disable endrx: end of receive transfer interrupt disable endtx: end of transmit interrupt disable ovre: overrun error interrupt disable frame: framing error interrupt disable pare: parity error interrupt disable timeout: time-out interrupt disable txempty: txempty interrupt disable iteration: iteration interrupt disable txbufe: buffer empty interrupt disable rxbuff: buffer full interrupt disable nack: non acknowledge interrupt disable riic: ring indicator input change disable dsric: data set ready input change disable dcdic: data carrier detect input change interrupt disable ctsic: clear to send input change interrupt disable mane: manchester error interrupt disable 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? mane ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
336 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.5 usart interrupt mask register name: us_imr access type: read-only rxrdy: rxrdy interrupt mask txrdy: txrdy interrupt mask rxbrk: receiver break interrupt mask endrx: end of receive transfer interrupt mask endtx: end of transmit interrupt mask ovre: overrun error interrupt mask frame: framing error interrupt mask pare: parity error interrupt mask timeout: time-out interrupt mask txempty: txempty interrupt mask iteration: iteration interrupt mask txbufe: buffer empty interrupt mask rxbuff: buffer full interrupt mask nack: non acknowledge interrupt mask riic: ring indicator input change mask dsric: data set ready input change mask dcdic: data carrier detect input change interrupt mask ctsic: clear to send input change interrupt mask mane: manchester error interrupt mask 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? mane ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
337 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.6 usart channel status register name: us_csr access type: read-only rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. endrx: end of receiver transfer 0: the end of transfer signal from the receive pdc channel is inactive. 1: the end of transfer signal from the receive pdc channel is active. endtx: end of transmitter transfer 0: the end of transfer signal from the transmit pdc channel is inactive. 1: the end of transfer signal from the transmit pdc channel is active. ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. 31 30 29 28 27 26 25 24 ???????manerr 23 22 21 20 19 18 17 16 cts dcd dsr ri ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
338 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary timeout: receiver time-out 0: there has not been a time-out since the last start time-out command or the time-out register is 0. 1: there has been a time-out since the last start time-out command. txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there is at least one character in either us_thr or the transmit shift register. iteration: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rsit. 1: maximum number of repetitions has been reached since the last rsit. txbufe: transmission buffer empty 0: the signal buffer empty from the transmit pdc channel is inactive. 1: the signal buffer empty from the transmit pdc channel is active. rxbuff: reception buffer full 0: the signal buffer full from the receive pdc channel is inactive. 1: the signal buffer full from th e receive pdc channel is active. nack: non acknowledge 0: no non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. riic: ring indicator input change flag 0: no input change has been detected on the ri pin since the last read of us_csr. 1: at least one input change has been detected on the ri pin since the last read of us_csr. dsric: data set ready input change flag 0: no input change has been detected on the dsr pin since the last read of us_csr. 1: at least one input change has been detected on the dsr pin since the last read of us_csr. dcdic: data carrier detect input change flag 0: no input change has been detected on the dcd pin since the last read of us_csr. 1: at least one input change has been detected on the dcd pin since the last read of us_csr. ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. ri: image of ri input 0: ri is at 0. 1: ri is at 1. dsr: image of dsr input 0: dsr is at 0 1: dsr is at 1. dcd: image of dcd input
339 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 0: dcd is at 0. 1: dcd is at 1. cts: image of cts input 0: cts is at 0. 1: cts is at 1. manerr: manchester error 0: no manchester error has been detected since the last rststa. 1: at least one manchester error has been detected since the last rststa.
340 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.7 usart receive holding register name: us_rhr access type: read-only rxchr: received character last character received if rxrdy is set. rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31.7.8 usart transmit holding register name: us_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ? ? ? ? ? ? rxchr 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ? ? ? ? ? ? txchr 76543210 txchr
341 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.9 usart baud rate generator register name: us_brgr access type: read/write cd: clock divider fp: fractional part 0: fractional divider is disabled. 1 - 7: baudrate resolution, defined by fp x 1/8. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? fp 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio
342 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.10 usart receiver time-out register name: us_rtor access type: read/write to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. 31.7.11 usart transmitter timeguard register name: us_ttgr access type: read/write tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
343 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.12 usart fi di ratio register name: us_fidi access type: read/write reset value : 0x174 fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31.7.13 usart number of errors register name: us_ner access type: read-only nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
344 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.14 usart manchester configuration register name: us_man access type: read/write tx_pl: transmitter preamble length 0: the transmitter preamble pattern generation is disabled 1 - 15: the preamble length is tx_pl x bit period tx_pp: transmitter preamble pattern tx_mpol: transmitter manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. rx_pl: receiver preamble length 0: the receiver preamble pattern detection is disabled 1 - 15: the detected preamble length is rx_pl x bit period rx_pp: receiver preamble pattern detected 31 30 29 28 27 26 25 24 ? drift ? rx_mpol ? ? rx_pp 23 22 21 20 19 18 17 16 ???? rx_pl 15 14 13 12 11 10 9 8 ? ? ? tx_mpol ? ? tx_pp 76543210 ???? tx_pl tx_pp preamble pattern default polari ty assumed (tx_mpol field not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero rx_pp preamble pattern de fault polarity assumed (rx_mpol fi eld not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero
345 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary rx_mpol: receiver manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. drift: drift compensation 0: the usart can not recover from an important clock drift 1: the usart can recover from clock drift. the 16x clock mode must be enabled.
346 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 31.7.15 usart irda filter register name: us_if access type: read/write irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
347 6120a?atarm?01-sep-05 at91samx256/128 preliminary 32. synchronous serial controller (ssc) 32.1 overview the atmel synchronous serial controller (ssc) provides a synchronous communication link with external devices. it supports many serial synchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. the transfers can be pro- grammed to start automatically or on different events detected on the frame sync signal. the ssc?s high-level of progra mmability and its two dedicated pdc channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. featuring connection to two pdc channels, the ssc permits interfacing with low processor overhead to the following: codec?s in master or slave mode dac through dedicated serial interface, particularly i2s magnetic card reader
348 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.2 block diagram figure 32-1. block diagram 32.3 application block diagram figure 32-2. application block diagram ssc interface pio pdc apb bridge mck asb apb tf tk td rf rk rd interrupt control ssc interrupt pmc interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
349 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.4 pin name list 32.5 product dependencies 32.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. before using the ssc receiver, the pio contro ller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio contro ller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. 32.5.2 power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. 32.5.3 interrupt the ssc interface has an interrupt line connected to the advanced interrupt controller (aic). handling interrupts requires programming the aic before configuring the ssc. all ssc interrupts can be enabled/disabled conf iguring the ssc interrupt mask register. each pending and unmasked ssc interr upt will assert the ssc interrupt line. th e ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. 32.6 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when trans- mission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be programmed to operate with the clo ck signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. table 32-1. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output
350 6120a?atarm?01-sep-05 at91sam9261 premliminary figure 32-3. ssc functional block diagram 32.6.1 clock management the transmitter clock can be generated by: an external clock received on the tk i/o pad the receiver clock the internal clock divider the receiver clock can be generated by: an external clock received on the rk i/o pad the transmitter clock the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave mode data transfers. interrupt control aic user interface apb mck receive clock controller start selector tx clock rk input rf tf clock output controller frame sync controller transmit clock controller transmit shift register start selector transmit sync holding register transmit holding register load shift rx clock tx clock tk input tf tx pdc rf rd rf rk clock output controller frame sync controller receive shift register receive sync holding register receive holding register load shift td tf tk rx clock rx pdc receiver pdc transmitter clock divider
351 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.6.1.1 clock divider figure 32-4. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode regi ster ssc_cmr, allowing a master clock divi- sion by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal to or greater than 1, the divided clock has a frequency of master clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50% duty cycle for the divided clock regard- less of whether the div value is even or odd. figure 32-5. divided clock generation 32.6.1.2 transmitter clock management the transmitter clock is generated from the receiv er clock or the divider clock or an external clock scanned on the tk i/o pad. the transmitte r clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. the transmitter can also drive the tk i/o pad continuously or be limited to the actual data transfer. the clock output is configured by the ssc_tcmr register. the transmit clock inver- sion (cki) bits have no effect on the clock outputs. programming the tcmr register to select mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6 table 32-2. maximum minimum mck / 2 mck / 8190
352 6120a?atarm?01-sep-05 at91sam9261 premliminary tk pin (cks field) and at the same time contin uous transmit clock (cko field) might lead to unpredictable results. figure 32-6. transmitter clock management 32.6.1.3 receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuously or be limited to the actual data trans- fer. the clock output is configured by the ss c_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) can lead to unpre- dictable results. figure 32-7. receiver clock management receiver clock divider clock transmitter clock ssc_tcmr.cki ssc_tcmr.cks tk ssc_tcmr.cko 1 0 tk transmitter clock divider clock receiver clock ssc_rcmr.cki ssc_rcmr.cks rk ssc_rcmr.cko 1 0 rk
353 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.6.1.4 serial clock ratio considerations the transmitter and the receiver can be programmed to operate with the clock signals pro- vided on either the tk or rk pins. this allo ws the ssc to support many slave-mode data transfers. in this case, the maximum clock speed allowed on the rk pin is: ? master clock divided by 2 if receiver frame synchro is input ? master clock divided by 3 if receiver frame synchro is output in addition, the maximum clock s peed allowed on the tk pin is: ? master clock divided by 6 if transmit frame synchro is input ? master clock divided by 2 if transmit frame synchro is output 32.6.2 transmitter operations a transmitted frame is triggered by a start even t and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see ?start? on page 354. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see ?frame sync? on page 356. to transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to the ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are empty, the status flag txempty is set in ssc_sr. when the transmit holding regi ster is transferred in the transmit shift reg- ister, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. figure 32-8. transmitter block diagram transmit shift register start selector ssc_tshr ssc_thr transmitter clock td ssc_tfmr.fslen ssc_tfmr.datlen ssc_cr.txen ssc_cr.txdis ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_sr.txen ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly ssc_tfmr.fsden 0 1 1 0 rf tf
354 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.6.3 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see ?start? on page 354. the frame synchronization is configured setting the receive frame mode register (ssc_rfmr). see ?frame sync? on page 356. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register depending on the data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the status flag rxrdy is set in ssc_sr and the data can be read in the receiver holding register. if another transfer occurs before read of the rh r register, the status flag overun is set in ssc_sr and the receiver shift register is transferred in the rhr register. figure 32-9. receiver block diagram 32.6.4 start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start selection (start) field of ssc_tcmr and in the receive start selection (start) field of ssc_rcmr. under the following conditions the start event is independently programmable: continuous. in this case, the transmission starts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. synchronously with the transmitter/receiver on detection of a falling/rising edge on tf/rf on detection of a low level/high level on tf/rf on detection of a level change or an edge on tf/rf receive shift register start selector ssc_rhr ssc_rshr receiver clock rd ssc_rfmr.fslen ssc_rfmr.datlen rf ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen ssc_rfmr.msbf ssc_rcmr.sttdly ssc_rfmr.datnb tf
355 6120a?atarm?01-sep-05 at91sam9261 premliminary a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start coul d be on tf (transmit) or rf (receive). moreover, the receiver can start when data is detected in the bit stream with the compare functions. detection on tf/rf input/output is done by the field fsos of the transmit/receive frame mode register (tfmr/rfmr). figure 32-10. transmit start mode figure 32-11. receive pulse/ed ge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf
356 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.6.5 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchronization signals. the frame sync output selection (fsos) field in the receive frame mode register (ssc_rfmr) and in the transmit frame mode register (ssc_tfmr) are used to select the required waveform. programmable low or high levels during data transfer are supported. programmable high levels before the start of data transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in ssc_rfmr and ssc_tfmr programs the length of the pulse, from 1 bit time up to 16 bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection ( period) field in ssc_rcmr and ssc_tcmr. 32.6.5.1 frame sync data frame sync data transmits or receives a specific tag during the frame sync signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer transmit sync holding regis- ter in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in ssc_rfmr/ssc_tfmr. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the receive sync holding register through the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the transmit register, then shifted out. 32.6.5.2 frame sync edge detection the frame sync edge detection is programmed by the fsedge field in ssc_rfmr/ssc_tfmr. this sets the corres ponding flags rxsyn/txsyn in the ssc sta- tus register (ssc_sr) on frame synchro edge detection (signals rf/tf). 32.6.6 receive compare modes figure 32-12. receive compare modes cmp0 cmp3 cmp2 cmp1 ignored b0 b2 b1 start rk rd (input) fslen up to 16 bits (4 in this example) stdly datlen
357 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.6.6.1 compare functions compare 0 can be one start event of the receiver. in this case, the receiver compares at each new sample the last fslen bits received at t he fslen lower bit of the data contained in the compare 0 register (ssc_rc0r). when this start event is selected, the user can program the receiver to start a new data transfer either by writing a new compare 0, or by receiving continuously until compare 1 occurs. this se lection is done with the bit (stop) in ssc_rcmr. 32.6.7 data format the data framing format of both the transmitter and the receiver are programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either case, the user can independently select: the event that starts the data transfer (start) the delay in number of bit periods between the start event and the first data bit ( sttdly ) the length of the data (datlen) the number of data to be transferred for each start event (datnb). the length of synchronization transferred for each start event (fslen) the bit sense: most or lowest significant bit first (msbf). additionally, the transmitter can be used to transfer synchronization and select the level driven on the td pin while not in data transfer operati on. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in ssc_tfmr.
358 6120a?atarm?01-sep-05 at91sam9261 premliminary figure 32-13. transmit and receive frame format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. table 32-3. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number of words transmitted in frame ssc_tfmr ssc_rfmr msbf most significant bit first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef
359 6120a?atarm?01-sep-05 at91sam9261 premliminary figure 32-14. transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. fsden value has no effect on the transmission. syncdata cannot be output in continuous mode. figure 32-15. receive frame format in continuous mode note: 1. sttdly is set to 0. 32.6.8 loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfm r. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. 32.6.9 interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable register) these registers enable and disable, re spectively, the corresponding interrupt by set- ting and clearing the corresponding bit in ssc_im r (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the aic. datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd
360 6120a?atarm?01-sep-05 at91sam9261 premliminary figure 32-16. interrupt block diagram 32.7 ssc application examples the ssc can support several serial communicati on modes used in audio or high speed serial links. some standard applications are shown in th e following figures. all se rial link applications supported by the ssc are not listed here. figure 32-17. audio application block diagram ssc_imr pdc interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync txbufe endtx rxbuff endrx clear ssc_ier ssc_idr ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb
361 6120a?atarm?01-sep-05 at91sam9261 premliminary figure 32-18. codec application block diagram figure 32-19. time slot application block diagram ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
362 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8 synchronous serial contro ller (ssc) user interface table 32-4. register mapping offset register register name access reset 0x0 control register ssc_cr write ? 0x4 clock mode register ssc_cmr read/write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register ssc_rcmr read/write 0x0 0x14 receive frame mode register ssc_rfmr read/write 0x0 0x18 transmit clock mode register ssc_tcmr read/write 0x0 0x1c transmit frame mode register ssc_tfmr read/write 0x0 0x20 receive holding register ssc_rhr read 0x0 0x24 transmit holding register ssc_thr write ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register ssc_rshr read 0x0 0x34 transmit sync. holding register ssc_tshr read/write 0x0 0x38 receive compare 0 register ssc_rc0r read/write 0x0 0x3c receive compare 1 register ssc_rc1r read/write 0x0 0x40 status register ssc_sr read 0x000000cc 0x44 interrupt enable register ssc_ier write ? 0x48 interrupt disable register ssc_idr write ? 0x4c interrupt mask register ssc_imr read 0x0 0x50-0xfc reserved ? ? ? 0x100- 0x124 reserved for peripheral data controller (pdc) ? ? ?
363 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.1 ssc control register name: ssc_cr access type: write-only rxen: receive enable 0: no effect. 1: enables receive if rxdis is not set. rxdis: receive disable 0: no effect. 1: disables receive. if a character is currently being re ceived, disables at end of current character reception. txen: transmit enable 0: no effect. 1: enables transmit if txdis is not set. txdis: transmit disable 0: no effect. 1: disables transmit. if a character is currently being transmitted, disables at end of current character transmission. swrst: software reset 0: no effect. 1: performs a software reset. has priority on any other bit in ssc_cr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 swrst?????txdistxen 76543210 ??????rxdisrxen
364 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.2 ssc clock mode register name: ssc_cmr access type: read/write div: clock divider 0: the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? div 76543210 div
365 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.3 ssc receive clock mode register name: ssc_rcmr access type: read/write cks: receive clock selection cko: receive clock output mode selection cki: receive clock inversion 0: the data inputs (data and frame sync signals) are sample d on receive clock falling edge . the frame sync signal out- put is shifted out on receive clock rising edge. 1: the data inputs (data and frame sync signals) are sample d on receive clock rising edge. the frame sync signal out- put is shifted out on receive clock falling edge. cki affects only the receive clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 stddly 15 14 13 12 11 10 9 8 ? ? ? stop start 76543210 ckg cki cko cks cks selected receive clock 0x0 divided clock 0x1 tk clock signal 0x2 rk pin 0x3 reserved cko receive clock output mode rk pin 0x0 none input-only 0x1 continuous receive clock output 0x2 receive clock only during data transfers output 0x3-0x7 reserved
366 6120a?atarm?01-sep-05 at91sam9261 premliminary ckg: receive clock gating selection start: receive start selection stop: receive stop selection 0: after completion of a data transfer when starting with a compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: after starting a receive with a compare 0, the receiver operates in a continuous mode until a compare 1 is detected. sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period sig nal is generated each 2 x (period+1) receive clock. ckg receive clock gating 0x0 none, continuous clock 0x1 receive clock enabled only if rf low 0x2 receive clock enabled only if rf high 0x3 reserved start receive start 0x0 continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 transmit start 0x2 detection of a low level on rf signal 0x3 detection of a high level on rf signal 0x4 detection of a falling edge on rf signal 0x5 detection of a rising edge on rf signal 0x6 detection of any level change on rf signal 0x7 detection of any edge on rf signal 0x8 compare 0 0x9-0xf reserved
367 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.4 ssc receive frame mode register name: ssc_rfmr access type: read/write datlen: data length 0: forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the receiver. if datlen is lower or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. loop: loop mode 0: normal operating mode. 1: rd is driven by td, rf is driven by tf and tk drives rk. msbf: most significant bit first 0: the lowest significant bit of the data register is sampled first in the bit stream. 1: the most significant bit of the data register is sampled first in the bit stream. datnb: data number per frame this field defines the number of data words to be received after each transfer start, which is equal to (datnb + 1). fslen: receive frame sync length this field defines the length of the receive frame sync signal and the number of bits sampled and stored in the receive sync data register. when this mode is selected by the start field in the receive clock mode register, it also deter- mines the length of the sampled data to be compared to the compare 0 or compare 1 register. pulse length is equal to (fslen + 1) receive clock periods. th us, if fslen is 0, the receive frame sync signal is gener- ated during one receive clock period. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 msbf ? loop datlen
368 6120a?atarm?01-sep-05 at91sam9261 premliminary fsos: receive frame sync output selection fsedge: frame sync edge detection determines which edge on frame sy nc will generate the in terrupt rxsyn in the ssc status register. fsos selected receive frame sync signal rf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
369 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.5 ssc transmit clock mode register name: ssc_tcmr access type: read/write cks: transmit clock selection cko: transmit clock output mode selection cki: transmit clock inversion 0: the data outpu ts (data and frame sync signals) are shifted out on tr ansmit clock falling edge . the frame sync signal input is sampled on transmit clock rising edge. 1: the data outputs (data and frame sync signals) are shifted out on transmit clock rising edge. the frame sync signal input is sampled on tran smit clock falling edge. cki affects only the transmit clock and not the output clock signal. ckg: transmit clock gating selection 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ckg cki cko cks cks selected transmit clock 0x0 divided clock 0x1 rk clock signal 0x2 tk pin 0x3 reserved cko transmit clock output mode tk pin 0x0 none input-only 0x1 continuous transmit clock output 0x2 transmit clock only during data transfers output 0x3-0x7 reserved ckg transmit clock gating 0x0 none, continuous clock 0x1 transmit clock enabled only if tf low 0x2 transmit clock enabled only if tf high 0x3 reserved
370 6120a?atarm?01-sep-05 at91sam9261 premliminary start: transmit start selection sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is inse rted between the start event and the actual start of transmission of data. when the transmitter is programmed to start sync hronously with the receiver, the delay is also applied. note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emit- ted instead of the end of tag. period: transmit period divider selection this field selects the divider to apply to the selected transmi t clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock. start transmit start 0x0 continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 receive start 0x2 detection of a low level on tf signal 0x3 detection of a high level on tf signal 0x4 detection of a falling edge on tf signal 0x5 detection of a rising edge on tf signal 0x6 detection of any level change on tf signal 0x7 detection of any edge on tf signal 0x8 - 0xf reserved
371 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.6 ssc transmit frame mode register name: ssc_tfmr access type: read/write datlen: data length 0: forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the transmit. if datlen is lower or equal to 7, data transfers are bytes, if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. datdef: data default value this bit defines the level driven on the td pin while out of tran smission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. msbf: most significant bit first 0: the lowest significant bit of the data register is shifted out first in the bit stream. 1: the most significant bit of the data register is shifted out first in the bit stream. datnb: data number per frame this field defines the number of data words to be transferred after each transfer start, which is equal to (datnb +1). fslen: transmit frame sync length this field defines the length of the transmit frame sync signal and the number of bits shifted out from the transmit sync data register if fsden is 1. pulse length is equal to (fslen + 1) transmit clock periods, i.e., the pulse length can range from 1 to 16 transmit clock periods. if fslen is 0, the transmit frame sync signal is generated during one transmit clock period. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 m s b f ? dat d e f dat l e n
372 6120a?atarm?01-sep-05 at91sam9261 premliminary fsos: transmit frame sync output selection fsden: frame sync data enable 0: the td line is driven with the default va lue during the transmi t frame sync signal. 1: ssc_tshr value is shifted out during the tran smission of the transmit frame sync signal. fsedge: frame sync edge detection determines which edge on frame sync will gene rate the interrupt tx syn (status register). fsos selected transmit frame sync signal tf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
373 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.7 ssc receive holding register name: ssc_rhr access type: read-only rdat: receive data right aligned regardless of the number of data bits defined by datlen in ssc_rfmr. 32.8.8 ssc transmit holding register name: ssc_thr access type: write-only tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
374 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.9 ssc receive synchronization holding register name: ssc_rshr access type: read-only rsdat: receive synchronization data 32.8.10 ssc transmit synchronization holding register name: ssc_tshr access type: read/write tsdat: transmit synchronization data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
375 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.11 ssc receive compare 0 register name: ssc_rc0r access type: read/write cp0: receive compare data 0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp0 76543210 cp0
376 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.12 ssc receive compare 1 register name: ssc_rc1r access type: read/write cp1: receive compare data 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp1 76543210 cp1
377 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.13 ssc status register name: ssc_sr access type: read-only txrdy: transmit ready 0: data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register (tsr). 1: ssc_thr is empty. txempty: transmit empty 0: data remains in ssc_thr or is currently transmitted from tsr. 1: last data written in ssc_thr has been loaded in tsr and last data loaded in tsr has been transmitted. endtx: end of transmission 0: the register ssc_tcr has not reached 0 since the last write in ssc_tcr or ssc_tncr. 1: the register ssc_tcr has reached 0 sinc e the last write in ssc_tcr or ssc_tncr. txbufe: transmit buffer empty 0: ssc_tcr or ssc_tncr have a value other than 0. 1: both ssc_tcr and ssc_tncr have a value of 0. rxrdy: receive ready 0: ssc_rhr is empty. 1: data has been received and loaded in ssc_rhr. ovrun: receive overrun 0: no data has been loaded in ssc_rhr wh ile previous data has not been read since the last read of the status register. 1: data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. endrx: end of reception 0: data is written on the receive counter register or receive ne xt counter register. 1: end of pdc transfer when receive counter register has arrived at zero. rxbuff: receive buffer full 0: ssc_rcr or ssc_rncr have a value other than 0. 1: both ssc_rcr and ssc_rncr have a value of 0. cp0: compare 0 0: a compare 0 has not occurred since the last read of the status register. 1: a compare 0 has occurred since the last read of the status register. cp1: compare 1 0: a compare 1 has not occurred since the last read of the status register. 1: a compare 1 has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????rxentxen 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
378 6120a?atarm?01-sep-05 at91sam9261 premliminary txsyn: transmit sync 0: a tx sync has not occurred since the last read of the status register. 1: a tx sync has occurred since the last read of the status register. rxsyn: receive sync 0: an rx sync has not occurred since the last read of the status register. 1: an rx sync has occurred since the last read of the status register. txen: transmit enable 0: transmit is disabled. 1: transmit is enabled. rxen: receive enable 0: receive is disabled. 1: receive is enabled.
379 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.14 ssc interrupt enable register name: ssc_ier access type: write-only txrdy: transmit ready interrupt enable 0: no effect. 1: enables the transmit ready interrupt. txempty: transmit empty interrupt enable 0: no effect. 1: enables the transmit empty interrupt. endtx: end of transmission interrupt enable 0: no effect. 1: enables the end of transmission interrupt. txbufe: transmit buffer empty interrupt enable 0: no effect. 1: enables the transmit buffer empty interrupt rxrdy: receive ready interrupt enable 0: no effect. 1: enables the receive ready interrupt. ovrun: receive overrun interrupt enable 0: no effect. 1: enables the receive overrun interrupt. endrx: end of reception interrupt enable 0: no effect. 1: enables the end of reception interrupt. rxbuff: receive buffer full interrupt enable 0: no effect. 1: enables the receive buffer full interrupt. cp0: compare 0 interrupt enable 0: no effect. 1: enables the compare 0 interrupt. cp1: compare 1 interrupt enable 0: no effect. 1: enables the compare 1 interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
380 6120a?atarm?01-sep-05 at91sam9261 premliminary txsyn: tx sync interrupt enable 0: no effect. 1: enables the tx sync interrupt. rxsyn: rx sync interrupt enable 0: no effect. 1: enables the rx sync interrupt.
381 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.15 ssc interrupt disable register name: ssc_idr access type: write-only txrdy: transmit ready interrupt disable 0: no effect. 1: disables the transmit ready interrupt. txempty: transmit empty interrupt disable 0: no effect. 1: disables the transmit empty interrupt. endtx: end of transmission interrupt disable 0: no effect. 1: disables the end of transmission interrupt. txbufe: transmit buffer empty interrupt disable 0: no effect. 1: disables the transmit buffer empty interrupt. rxrdy: receive ready interrupt disable 0: no effect. 1: disables the rece ive ready interrupt. ovrun: receive overrun interrupt disable 0: no effect. 1: disables the receive overrun interrupt. endrx: end of reception interrupt disable 0: no effect. 1: disables the end of reception interrupt. rxbuff: receive buffer full interrupt disable 0: no effect. 1: disables the receiv e buffer full interrupt. cp0: compare 0 interrupt disable 0: no effect. 1: disables the compare 0 interrupt. cp1: compare 1 interrupt disable 0: no effect. 1: disables the compare 1 interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
382 6120a?atarm?01-sep-05 at91sam9261 premliminary txsyn: tx sync interrupt enable 0: no effect. 1: disables the tx sync interrupt. rxsyn: rx sync interrupt enable 0: no effect. 1: disables the rx sync interrupt.
383 6120a?atarm?01-sep-05 at91sam9261 premliminary 32.8.16 ssc interrupt mask register name: ssc_imr access type: read-only txrdy: transmit ready interrupt mask 0: the transmit ready interrupt is disabled. 1: the transmit ready interrupt is enabled. txempty: transmit empty interrupt mask 0: the transmit empty interrupt is disabled. 1: the transmit empty interrupt is enabled. endtx: end of transmission interrupt mask 0: the end of transmission interrupt is disabled. 1: the end of transmission interrupt is enabled. txbufe: transmit buffer empty interrupt mask 0: the transmit buffer empty interrupt is disabled. 1: the transmit buffer empty interrupt is enabled. rxrdy: receive ready interrupt mask 0: the receive ready interrupt is disabled. 1: the receive ready interrupt is enabled. ovrun: receive overrun interrupt mask 0: the receive overrun interrupt is disabled. 1: the receive overrun interrupt is enabled. endrx: end of reception interrupt mask 0: the end of reception interrupt is disabled. 1: the end of reception interrupt is enabled. rxbuff: receive buffer full interrupt mask 0: the receive buffer full interrupt is disabled. 1: the receive buffer full interrupt is enabled. cp0: compare 0 interrupt mask 0: the compare 0 interrupt is disabled. 1: the compare 0 interrupt is enabled. cp1: compare 1 interrupt mask 0: the compare 1 interrupt is disabled. 1: the compare 1 interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuf endrx ovrun rxrdy txbufe endtx txempty txrdy
384 6120a?atarm?01-sep-05 at91sam9261 premliminary txsyn: tx sync interrupt mask 0: the tx sync interrupt is disabled. 1: the tx sync interrupt is enabled. rxsyn: rx sync interrupt mask 0: the rx sync interrupt is disabled. 1: the rx sync interrupt is enabled.
385 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33. timer/counter (tc) 33.1 overview the timer/counter (tc) includes three identical 16-bit timer/counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. the timer/counter block has two global registers which act upon all three (or two) tc channels. the block control register allows the three (or two) channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. 33.2 block diagram figure 33-1. timer/counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 advanced interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1
386 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.3 pin name list 33.4 product dependencies 33.4.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 33.4.2 power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer/counter clock. 33.4.3 interrupt the tc has an interrupt line connected to the advanced interrupt controller (aic). handling the tc interrupt requires programming the aic before configuring the tc. table 33-1. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: ti mer/counter input waveform mode: timer/counter output tiob capture mode: ti mer/counter input waveform mode: timer/counter input/output int interrupt signal output sync synchronization input signal table 33-2. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o
387 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.5 functional description 33.5.1 tc description the three channels of the timer/counter are independent and identical in operation. the regis- ters for channel programming are listed in table 33-4 on page 400 . 33.5.1.1 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 33.5.1.2 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to th e configurable i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 33-2 . each channel can independently select an internal or external clock source for its counter: internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be validat ed when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). note: in all cases, if an external clock is used, the du ration of each of its leve ls must be longer than the master clock period. the external clock frequen cy must be at least 2.5 times lower than the mas- ter clock
388 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 33-2. clock selection 33.5.1.3 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 33-3 . the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock
389 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 33-3. clock control 33.5.1.4 tc operating modes each channel can independently operate in two different modes: capture mode provides measurement on signals. waveform mode provides wave generation. the tc operating mode is prog rammed with the wave bit in th e tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 33.5.1.5 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc value if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
390 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 33.5.2 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob sig nals which are considered as inputs. figure 33-4 shows the configuration of the tc channel when programmed in capture mode. 33.5.2.1 capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a progr ammable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. 33.5.2.2 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trig- ger can be defined. the abetrg bit in tc_cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the ed ge (rising, falling or both) detec ted to generate an external trigger. if etrgedg = 0 (none), the external trigger is disabled.
391 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 33-4. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel
392 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.5.3 waveform operating mode waveform operating mode is entered by setting the wave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same fre- quency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event ( eevt parameter in tc_cmr). figure 33-5 shows the configuration of the tc channel when programmed in waveform operat- ing mode. 33.5.3.1 waveform selection depending on the wavsel parameter in tc_c mr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
393 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 33-5. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel
394 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.5.3.2 wavsel = 00 when wavsel = 00, the value of tc_cv is incr emented from 0 to 0x ffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 33-6 . an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 33-7 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 33-6. wavsel= 00 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples
395 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 33-7. wavsel= 00 with trigger 33.5.3.3 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, then auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 33-8 . it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 33-9 . in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger
396 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 33-8. wavsel = 10 without trigger figure 33-9. wavsel = 10 with trigger 33.5.3.4 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 33-10 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 33-11 . time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
397 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). figure 33-10. wavsel = 01 without trigger figure 33-11. wavsel = 01 with trigger 33.5.3.5 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 33-12 . time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
398 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 33-13 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpc- dis = 1). figure 33-12. wavsel = 11 without trigger figure 33-13. wavsel = 11 with trigger 33.5.3.6 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
399 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the parameter eevt parameter in tc_cmr selects the external trigger. the eevtedg param- eter defines the trigger edge for each of the possible external triggers (rising, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. 33.5.3.7 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr.
400 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6 timer/counter (tc) user interface 33.6.1 global register mapping tc_bcr (block control register) and tc_bmr (b lock mode register) control the whole tc block. tc channels are controlled by the registers listed in table 33-4 . the offset of each of the channel registers in table 33-4 is in relation to the offset of the corresponding channel as men - tioned in table 33-4 . 33.6.2 channel memory mapping note: 1. read only if wave = 0 table 33-3. timer/counter (tc) global register map offset channel/register name access reset value 0x00 tc channel 0 see table 33-4 0x40 tc channel 1 see table 33-4 0x80 tc channel 2 see table 33-4 0xc0 tc block control register tc_bcr write-only ? 0xc4 tc block mode register tc_bmr read/write 0 table 33-4. timer/counter (tc) channel memory mapping offset register name access reset value 0x00 channel control register tc_ccr write-only ? 0x04 channel mode register tc_cmr read/write 0 0x08 reserved ? ? ? 0x0c reserved ? ? ? 0x10 counter value tc_cv read-only 0 0x14 register a tc_ra read/write (1) 0 0x18 register b tc_rb read/write (1) 0 0x1c register c tc_rc read/write 0 0x20 status register tc_sr read-only 0 0x24 interrupt enable register tc_ier write-only ? 0x28 interrupt disable register tc_idr write-only ? 0x2c interrupt mask register tc_imr read-only 0 0x30-0xfc reserved ? ? ?
401 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.3 tc block control register register name: tc_bcr access type: write-only sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync
402 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.4 tc block mode register register name: tc_bmr access type: read/write tc0xc0s: external clock signal 0 selection tc1xc1s: external clock signal 1 selection tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? tc2xc2s tcxc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 0 1 none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2 tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1
403 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.5 tc channel control register register name: tc_ccr access type: write-only clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????swtrgclkdisclken
404 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.6 tc channel mode register: capture mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. ldbdis: counter clock disable with rb loading 0 = counter clock is not disabl ed when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? ldrb ldra 15 14 13 12 11 10 9 8 wave = 0 cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks tcclks clock selected 000timer_clock1 001timer_clock2 010timer_clock3 011timer_clock4 100timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
405 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary etrgedg: external trigger edge selection abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ldra: ra loading selection ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa
406 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.7 tc channel mode register: waveform mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. cpcdis: counter clock disable with rc compare 0 = counter clock is not disabl ed when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave = 1 wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks tcclks clock selected 000timer_clock1 001timer_clock2 010timer_clock3 011timer_clock4 100timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
407 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary eevtedg: external ev ent edge selection eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is configured as an input and no longer generates waveforms . enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. wavsel: waveform selection wave = 1 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. acpa: ra compare effect on tioa eevtedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as exte rnal event tiob direction 0 0 tiob input (1) 01xc0 output 10xc1 output 11xc2 output wavsel effect 0 0 up mode without automatic trigger on rc compare 1 0 up mode with automa tic trigger on rc compare 0 1 updown mode without automatic trigger on rc compare 1 1 updown mode with automatic trigger on rc compare acpa effect 0 0 none 0 1 set 1 0 clear 1 1 toggle
408 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary acpc: rc compare effect on tioa aeevt: external event effect on tioa aswtrg: software trigger effect on tioa bcpb: rb compare effect on tiob bcpc: rc compare effect on tiob acpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aeevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle
409 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary beevt: external event effect on tiob bswtrg: software trigger effect on tiob beevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle
410 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.8 tc counter value register register name: tc_cv access type: read-only cv: counter value cv contains the counter value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv
411 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.9 tc register a register name: tc_ra access type: read-only if wave = 0, read/write if wave = 1 ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra
412 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.10 tc register b register name: tc_rb access type: read-only if wave = 0, read/write if wave = 1 rb: register b rb contains the register b value in real time. 33.6.11 tc register c register name: tc_rc access type: read/write rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc
413 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.12 tc status register register name: tc_sr access type: read-only covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ldras: ra loading status 0 = ra load has not occurred si nce the last read of the status register or wave = 1. 1 = ra load has occurred since the last re ad of the status register, if wave = 0. ldrbs: rb loading status 0 = rb load has not occurred si nce the last read of the status register or wave = 1. 1 = rb load has occurred since the last re ad of the status register, if wave = 0. etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
414 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary mtioa: tioa mirror 0 = tioa is low. if wave = 0, this mean s that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this mean s that tioa pin is high. if wave = 1, this means that ti oa is driven high. mtiob: tiob mirror 0 = tiob is low. if wave = 0, this mean s that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this mean s that tiob pin is high. if wave = 1, this means that ti ob is driven high.
415 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.13 tc interrupt enable register register name: tc_ier access type: write-only covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
416 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.14 tc interrupt disable register register name: tc_idr access type: write-only covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = disables the load overru n interrupt (if wave = 0). cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
417 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 33.6.15 tc interrupt mask register register name: tc_imr access type: read-only covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
418 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary
419 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34. pulse width modulation controller (pwm) 34.1 overview the pwm macrocell controls several cha nnels independently. each channel controls one square output waveform. characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. each channel selects and uses one of the clocks provided by the clock generator. the clock generator provides several clocks resulting from the division of the pwm macrocell master clock. all pwm macrocell accesses are made through apb mapped registers. channels can be synchronized, to generate non overlapped waveforms. all channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. 34.2 block diagram figure 34-1. pulse width modulation controller block diagram pwm controller apb pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio aic pmc mck clock generator apb interface interrupt generator clock selector period comparator update duty cycle counter clock selector period comparator pwm0 pwm0
420 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.3 i/o lines description each channel outputs one waveform on one external i/o line. 34.4 product dependencies 34.4.1 i/o lines the pins used for interfacing the pwm may be multiplexed with pio lines. the programmer must first program the pio controller to assign the desire d pwm pins to their peripheral function. if i/o lines of the pwm are not used by the applicati on, they can be used for other purposes by the pio controller. all of the pwm outputs may or may not be enabled. if an application requires only four channels, then only four pio lines will be assigned to pwm outputs. 34.4.2 power management the pwm is not continuously clocked. the programmer must first enable the pwm clock in the power management controller (pmc) before using the pwm. however, if the application does not require pwm operations, the pwm clock can be stopped when not needed and be restarted later. in this case, th e pwm will resume its operat ions where it left off. configuring the pwm does not require the pwm clock to be enabled. 34.4.3 interrupt sources the pwm interrupt line is connected on one of the internal sources of the advanced interrupt controller. using the pwm interrupt requires the ai c to be programmed first. note that it is not recommended to use the pwm interrupt line in edge sensitive mode. table 34-1. i/o line description name description type pwmx pwm waveform output for channel x output
421 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.5 functional description the pwm macrocell is primarily composed of a clock generator module and 4 channels. clocked by the system clock, mck, the clock generator module provides 13 clocks. each channel can independently choose one of the clock generator outputs. each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 34.5.1 pwm clock generator figure 34-2. functional view of the clock generator block diagram caution: before using the pwm macrocell, the prog rammer must first enable the pwm clock in the power management controller (pmc). the pwm macrocell master clock, mck, is divide d in the clock generator module to provide dif- ferent clocks available for all channels. each channel can independently select one of the divided clocks. the clock generator is divided in three blocks: a modulo n counter which provides 11 clocks: f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /128, f mck /256, f mck /512, f mck /1024 two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clka and clkb modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb
422 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary each linear divider can independently divide one of the clocks of the modulo n counter. the selection of the clock to be divided is made ac cording to the prea (preb) field of the pwm mode register (pwm_mr). the resulting clock clka (clkb) is the clock selected divided by diva (divb) field value in the pwm mode register (pwm_mr). after a reset of the pwm controller, diva (divb) and prea (preb) in the pwm mode register are set to 0. this implies that after reset clka (clkb) are turned off. at reset, all clocks provided by the modulo n counter are turned off except clock ?clk?. this situa- tion is also true when the pwm master cloc k is turned off through the power management controller. 34.5.2 pwm channel 34.5.2.1 block diagram figure 34-3. functional view of the channel block diagram each of the 4 channels is composed of three blocks: a clock selector which selects one of the clocks provided by the clock generator described in section 34.5.1 ?pwm clock generator?, on page 421 . an internal counter clocked by the output of the clock selector. this internal counter is incremented or decremented according to the channel configuration and comparators events. the size of the internal counter is 16 bits. a comparator used to generate events according to the internal counter value. it also computes the pwmx output waveform according to the configuration. 34.5.2.2 waveform properties the different properties of output waveforms are: the internal clock selection . the internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. this channel parameter is defined in the cpre field of the pwm_cmrx register. this field is reset at 0. the waveform period . this channel parameter is defined in the cprd field of the pwm_cprdx register. - if the waveform is left aligned, then the output waveform period depends on the counter source clock and can be claculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: comparator pwmx output waveform internal counter clock selector channel inputs from clock generator inputs from apb bus xcprd () mck --------------------------------
423 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary by using a master clock divided by one of bo th diva or divb divider, the formula becomes, respectively: or if the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the re sulting period formula will be: by using a master clock divided by one of bo th diva or divb divider, the formula becomes, respectively: or the waveform duty cycle . this channel parameter is defined in the cdty field of the pwm_cdtyx register. if the waveform is left aligned then: if the waveform is center aligned, then: the waveform polarity. at the beginning of the period, the signal can be at high or low level. this property is defined in the cpol field of the pwm_cmrx register. by default the signal starts by a low level. the waveform alignment . the output waveform can be left or center aligned. center aligned waveforms can be used to generate non overlapped waveforms. this property is defined in the calg field of the pwm_cmrx register. the default mode is left aligned. figure 34-4. non overlapped center aligned waveforms (1) note: 1. see figure 34-5 on page 425 for a detailed description of center aligned waveforms. crpd diva () mck ------------------------------------------- crpd divab () mck ----------------------------------------------- 2 xcprd () mck ------------------------------------------ - 2 cprd diva () mck ----------------------------------------------------- - 2 cprd divb () mck ----------------------------------------------------- - d uty cycle period 1 fchannel_x_clock cdty ? ? ( ) period ---------------------------------------------------------------------------------------------------------- - - = uty cycle period 2 ? () 1 fchannel_x_clock cdty ? ? () period 2 ? () --------------------------------------------------------------------------------------------------------------------------- - = pwm0 pwm1 period no overlap
424 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary when center aligned, the internal channel c ounter increases up to cprd and decreases down to 0. this ends the period. when left aligned, the internal channel counter increases up to cprd and is reset. this ends the period. thus, for the same cprd value, the period for a ce nter aligned channel is twice the period for a left aligned channel. waveforms are fixed at 0 when: cdty = cprd and cpol = 0 cdty = 0 and cpol = 1 waveforms are fixed at 1 (once the channel is enabled) when: cdty = 0 and cpol = 0 cdty = cprd and cpol = 1 the waveform polarity must be set before enabling the channel. this immediately affects the channel output level. changes on channel polari ty are not taken into account while the channel is enabled.
425 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 34-5. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis)
426 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.5.3 pwm controller operations 34.5.3.1 initialization before enabling the output channel, this channel must have been configured by the software application: configuration of the clock generator if diva and divb are required selection of the clock for each channel (cpre field in the pwm_cmrx register) configuration of the waveform alignment for each channel (calg field in the pwm_cmrx register) configuration of the period for each channel (cprd in the pwm_cprdx register). writing in pwm_cprdx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cprdx as explained below. configuration of the duty cycl e for each channel (cdty in the pwm_cdtyx register). writing in pwm_cdtyx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cdtyx as explained below. configuration of the output waveform polarity for each channel (cpol in the pwm_cmrx register) enable interrupts (writing chidx in the pwm_ier register) enable the pwm channel (writing chidx in the pwm_ena register) it is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several chidx bits in the pwm_ena register. in such a situation, all channels may have the same clock selector configuration and the same period specified. 34.5.3.2 source clock selection criteria the large number of source clocks can make selection difficult. the relationship between the value in the period register (pwm_cprdx) an d the duty cycle regi ster (pwm_cdtyx) can help the user in choosing. the event number written in the period register gives the pwm accu- racy. the duty cycle quantum cannot be lower than 1/pwm_cprdx value. the higher the value of pwm_cprdx, the greater the pwm accuracy. for example, if the user sets 15 (in decimal) in pwm_cprdx, the user is able to set a value between 1 up to 14 in pwm_cdtyx register. the resulting duty cycle quantum cannot be lower than 1/15 of the pwm period. 34.5.3.3 changing the duty cycle or the period it is possible to modulate the output waveform duty cycle or period. to prevent an unexpected output waveform when modifying the waveform parameters while the channel is still enabled, pwm_cprdx and pwm_ cdtyx registers are double buffered. the user can write a new period value or duty cycl e value in the update register (pwm_cupdx). this register holds the new value until the end of the current cycle and updates the value for the next cycle. according to the cpd field in t he pwm_cmrx register, pwm_cupdx either updates the pwm_cprdx or pwm_cdtyx.
427 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 34-6. synchronized period or duty cycle update to prevent overwriting the pwm_cupdx by software , the user can use status events in order to synchronize his software. two methods are possible. in both, the user must enable the dedi- cated interrupt in pwm_ier at pwm controller level. the first method ( polling method) consists of reading the relevant status bit in pwm_isr regis- ter according to the enabled channel(s). see figure 34-7 . the second method uses an interrupt service routine associated with the pwm channel. note: reading the pwm_isr register automatically clears chidx flags. figure 34-7. polling method note: polarity and alignment can be modified only when the channel is disabled. pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes
428 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.5.3.4 interrupts depending on the interrupt mask in the pwm_imr register, an interrupt is generated at the end of the corresponding channel period. the interrupt remains active until a read operation in the pwm_isr register occurs. a channel interrupt is enabled by setting the corresponding bit in the pwm_ier register. a chan- nel interrupt is disabled by setting the corresponding bit in the pwm_idr register.
429 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6 pulse width modulation cont roller (pwm) user interface table 34-2. pulse width modulation controller (pwm) register mapping offset register name access peripheral reset value 0x00 pwm mode register pwm_mr read/write 0 0x04 pwm enable register pwm_ena write-only - 0x08 pwm disable register pwm_dis write-only - 0x0c pwm status register pwm_sr read-only 0 0x10 pwm interrupt enable register pwm_ier write-only - 0x14 pwm interrupt disable register pwm_idr write-only - 0x18 pwm interrupt mask register pwm_imr read-only 0 0x1c pwm interrupt status register pwm_isr read-only 0 0x4c - 0xfc reserved ? ? ? 0x100 - 0x1fc reserved 0x200 channel 0 mode register pwm_cmr0 read/write 0x0 0x204 channel 0 duty cycle register pwm_cdty0 read/write 0x0 0x208 channel 0 period register pwm_cprd0 read/write 0x0 0x20c channel 0 counter register pwm_ccnt0 read-only 0x0 0x210 channel 0 update register pwm_cupd0 write-only - ... reserved 0x220 channel 1 mode register pwm_cmr1 read/write 0x0 0x224 channel 1 duty cycle register pwm_cdty1 read/write 0x0 0x228 channel 1 period register pwm_cprd1 read/write 0x0 0x22c channel 1 counter register pwm_ccnt1 read-only 0x0 0x230 channel 1 update register pwm_cupd1 write-only - ... ... ... ... ...
430 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.1 pwm mode register register name: pwm_mr access type: read/write diva, divb: clka, clkb divide factor prea, preb 31 30 29 28 27 26 25 24 ???? preb 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 ???? prea 76543210 diva diva, divb clka, clkb 0 clka, clkb clock is turned off 1 clka, clkb clock is clock selected by prea, preb 2-255 clka, clkb clock is clock selected by prea, preb divided by diva, divb factor. prea, preb divider input clock 0000mck. 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1010mck/ 1024 other reserved
431 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.2 pwm enable register register name: pwm_ena access type: write-only chidx: channel id 0 = no effect. 1 = enable pwm output for channel x. 34.6.3 pwm disable register register name: pwm_dis access type: write-only chidx: channel id 0 = no effect. 1 = disable pwm output for channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
432 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.4 pwm status register register name: pwm_sr access type: read-only chidx: channel id 0 = pwm output for channel x is disabled. 1 = pwm output for channel x is enabled. 34.6.5 pwm interrupt enable register register name: pwm_ier access type: write-only chidx: channel id. 0 = no effect. 1 = enable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
433 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.6 pwm interrupt disable register register name: pwm_idr access type: write-only chidx: channel id. 0 = no effect. 1 = disable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
434 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.7 pwm interrupt mask register register name: pwm_imr access type: read-only chidx: channel id. 0 = interrupt for pwm channel x is disabled. 1 = interrupt for pwm channel x is enabled. 34.6.8 pwm interrupt status register register name: pwm_isr access type: read-only chidx: channel id 0 = no new channel period has been achieved si nce the last read of the pwm_isr register. 1 = at least one new channel period has been achiev ed since the last read of the pwm_isr register. note: reading pwm_isr automatically clears chidx flags. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
435 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.9 pwm channel mode register register name: pwm_cmrx access type: read/write cpre: channel pre-scaler calg: channel alignment 0 = the period is left aligned. 1 = the period is center aligned. cpol: channel polarity 0 = the output waveform starts at a low level. 1 = the output waveform starts at a high level. cpd: channel update period 0 = writing to the pwm_cupdx will modify the duty cycle at the next period start event. 1 = writing to the pwm_cupdx will modify th e period at the next period start event. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????cpdcpolcalg 76543210 ???? cpre cpre channel pre-scaler 0000mck 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1010mck/ 1024 1011clka 1100clkb other reserved
436 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.10 pwm channel duty cycle register register name: pwm_ cdty x access type: read/write only the first 16 bits (internal ch annel counter size) are significative. cdty: channel duty cycle defines the waveform duty cycle. this value must be defined between 0 and cprd (pwm_cprx). 34.6.11 pwm channel period register register name: pwm_cprdx access type: read/write only the first 16 bits (internal ch annel counter size) are significative. cprd: channel period if the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resu lting period formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 76543210 cdty 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 76543210 cprd xcprd () mck --------------------------------
437 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary or if the waveform is center-aligned, then the output waveform period depends on the counter source clockand can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024) . the resulting pe riod formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or crpd diva () mck ------------------------------------------- crpd divab () mck ----------------------------------------------- 2 xcprd () mck ------------------------------------------ - 2 cprd diva () mck ----------------------------------------------------- - 2 cprd divb () mck ----------------------------------------------------- -
438 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 34.6.12 pwm channel counter register register name: pwm_ccntx access type: read-only cnt: channel counter register internal counter value. this register is reset when: ? the channel is enabled (writing chidx in the pwm_ena register). ? the counter reaches cprd value defined in the pwm_ cprdx register if the waveform is left aligned. 34.6.13 pwm channel update register register name: pwm_cupdx access type: write-only this register acts as a double buffer for the period or the du ty cycle. this prevents an unexpected waveform when modify- ing the waveform period or duty-cycle. only the first 16 bits (internal chan nel counter size) are significative. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 76543210 cnt 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 76543210 cupd cpd (pwm_cmrx register) 0 the duty-cycle (cdtc in the pwm_cdrx regist er) is updated with the cupd value at the beginning of the next period. 1 the period (cprd in the pwm_cprx register) is updated with the cupd value at the beginning of the next period.
439 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35. usb device port (udp) 35.1 description the usb device port (udp) is compliant with the universal serial bus (usb) v2.0 full-speed device specification. each endpoint can be configured in one of several usb transfer types. it can be associated with one or two banks of a dual-port ram used to store the current data payload. if two banks are used, one dpr bank is read or written by the proc essor, while the other is read or written by the usb device peripheral. this feature is mandator y for isochronous endpoints. thus the device maintains the maximum bandwidth (1m bytes/s) by working with endpoints with two banks of dpr. suspend and resume are automatically detected by the usb device, which notifies the proces- sor by raising an interrupt. depending on the product, an external signal can be used to send a wake-up to the u sb host controller. table 35-1. usb endpoint description endpoint number mnemonic dual-bank max. endpoint size endpoint type 0 ep0 no 8 control/bulk/interrupt 1 ep1 yes 64 bulk/iso/interrupt 3 ep2 yes 64 bulk/iso/interrupt 3 ep3 no 64 control/bulk/interrupt 4 ep4 yes 256 bulk/iso/interrupt 5 ep5 yes 256 bulk/iso/interrupt
440 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.2 block diagram figure 35-1. block diagram access to the udp is via the apb bus interface. read and write to the data fi fo are done by reading and writing 8-bit values to apb registers. the udp peripheral requires two clocks: one peripheral clock used by the mck domain and a 48 mhz clock used by the 12 mhz domain. a usb 2.0 full-speed pad is embedded and controlled by the serial interface engine (sie). the signal external_resume is optional. it allows the udp peripheral to wake-up once in system mode. the host is then notified that the device asks for a resume. this optional feature must be also negotiated with the host during the enumeration. 35.3 product dependencies for further details on the usb device hardware implementation, see the specific product prop- erties document. the usb physical transceiver is integrated into the product. the bidirectional differential signals dp and dm are available from the product boundary. two i/o lines may be used by the application: one to check that vbus is still available from the host. self-powered devices may use this entry to be notified that the host has been powered off. in this case, the board pull-up on dp must be disabled in order to prevent feeding current to the host. one to control the board pull-up on dp. thus, when the device is ready to communicate with the host, it activates its dp pu ll-up through this control line. atmel bridge 12 mhz suspend/resume logic w r a p p e r w r a p p e r u s e r i n t e r f a c e serial interface engine sie mck master clock domain dual port ram fifo udpck recovered 12 mhz domain udp_int usb device embedded usb transceiver dp dm external_resume apb to mcu bus txoen eopn txd rxdm rxd rxdp
441 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.3.1 i/o lines dp and dm are not controlled by any pio controllers. the embedded usb physical transceiver is controlled by the usb device peripheral. to reserve an i/o line to check vbus, the progra mmer must first program the pio controller to assign this i/o in input pio mode. to reserve an i/o line to control the board pull-up, the programmer must first program the pio controller to assign this i/o in output pio mode. 35.3.2 power management the usb device peripheral requires a 48 mhz cl ock. this clock must be generated by a pll with an accuracy of 0.25%. thus, the usb device receives two clocks from the power management controller (pmc): the master clock, mck, used to drive the peripheral user interface, and the udpck, used to inter- face with the bus usb signals (recovered 12 mhz domain). 35.3.3 interrupt the usb device interface has an interrupt line co nnected to the advanced interrupt controller (aic). handling the usb device interrupt requires programming the aic before configuring the udp.
442 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.4 typical connection figure 35-2. board schematic to interface usb device peripheral udp_ cnx is an input signal used to check if the host is connected udp_ pup is an output signal used to disable pull-up on dp by driving it to 0. figure 35-2 shows automatic activation of pull-up after reset. 3v3 15 pf 15 pf 27 ? 33 pf 1.5 k ? 47 k ? 100 nf dm dp pan pam system reset 15 k ? 22 k ? 27 ? type b connector 1 2 34 udp_cnx udp_pup
443 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.5 functional description 35.5.1 usb v2.0 full-speed introduction the usb v2.0 full-speed provides communication services between host and attached usb devices. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with an usb device through a set of com- munication flows. figure 35-3. example of usb v2.0 full-speed communication control 35.5.1.1 usb v2.0 full-speed transfer types a communication flow is carried over one of f our transfer types defined by the usb device. 35.5.1.2 usb bus transactions each transfer results in one or more transactions over the usb bus. there are five kinds of transactions flowing acro ss the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 4. status in transaction 5. status out transaction ep0 usb host v2.0 software client 1 software client 2 data flow: bulk out transfer data flow: bulk in transfer data flow: control transfer data flow: control transfer ep1 ep2 usb device 2.0 block 1 usb device 2.0 block 2 ep5 ep4 ep0 data flow: isochronous in transfer data flow: isochronous out transfer table 35-2. usb communication flow transfer direction bandw idth endpoint size error detection retrying control bidirectional not guaranteed 8, 16, 32, 64 yes automatic isochronous unidirectional guaranteed 1 - 1023 yes no interrupt unidirectional not guaranteed 64 yes yes bulk unidirectional not guaranteed 8, 16, 32, 64 yes yes
444 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.5.1.3 usb transfer event definitions as indicated below, transfers are sequential events carried out on the usb bus. notes: 1. control transfer must use endpoints with no ping-pong attributes. 2. isochronous transfers must use endpoints with ping-pong attributes. 3. control transfers can be aborted using a stall handshake. 35.5.2 handling transactions with usb v2.0 device peripheral 35.5.2.1 setup transaction setup is a special type of host-to-device transaction used during control transfers. control trans- fers must be performed using endpoints with no ping-pong attributes. a setup transaction needs to be handled as soon as possible by the firmware. it is used to transmit requests from the host to the device. these requests are then handled by the usb device and may require more argu- ments. the arguments are sent to the device by a data out transaction which follows the setup transaction. these requests may also return data. the data is carried out to the host by the next data in transaction which follows the setup transaction. a status transaction ends the control transfer. when a setup transfer is received by the usb endpoint: the usb device automatically acknowledges the setup packet rxsetup is set in the udp_ csrx register an endpoint interrupt is generated while the rxsetup is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must detect th e rxsetup polling the udp_ csrx or catching an interrupt, read the setup packet in the fifo , then clear the rxsetup. rxsetup cannot be clear ed before the setup packet has been read in the fifo. otherwise, the usb device would accept the next data out transfer and overwrite the setup packet in the fifo. table 35-3. usb transfer events control transfers (1) (3) setup transaction > data in transactions > status out transaction setup transaction > data out transactions > status in transaction setup transaction > status in transaction interrupt in transfer (device toward host) data in transaction > data in transaction interrupt out transfer (host toward device) data out transaction > data out transaction isochronous in transfer (2) (device toward host) data in transaction > data in transaction isochronous out transfer (2) (host toward device) data out transaction > data out transaction bulk in transfer (device toward host) data in transaction > data in transaction bulk out transfer (host toward device) data out transaction > data out transaction
445 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 35-4. setup transaction followed by a data out transaction 35.5.2.2 data in transaction data in transactions are used in control, is ochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. data in transactions in isochronous transfer must be done using endpoints with ping-pong attributes. 35.5.2.3 using endpoints without ping-pong attributes to perform a data in transaction using a non ping-pong endpoint: 1. the microcontroller checks if it is possibl e to write in the fifo by polling txpktrdy in the endpoint?s udp_ csrx register (txpktrdy must be cleared). 2. the microcontroller writes data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s udp_ fdrx register, 3. the microcontroller notifies the usb peripheral it has finished by setting the txpk- trdy in the endpoint?s udp_ csrx register. 4. the microcontroller is notified that the endpoint?s fifo has been released by the usb device when txcomp in the endpoint?s udp_ csrx register has been set. then an interrupt for the corresponding endpoint is pending while txcomp is set. txcomp is set by the usb device when it has received an ack pid signal for the data in packet. an interrupt is pending while txcomp is set. note: refer to chapter 8 of the universal serial bus specification, rev 2.0, for more information on the data in protocol layer. rx_data_bko (udp_csrx) ack pid data out data out pid nak pid ack pid data setup setup pid usb bus packets rxsetup flag set by usb device cleared by firmware set by usb device peripheral fifo (dpr) content data setup data xx xx out interrupt pending setup received setup handled by firmware data out received data out data out pid
446 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 35-5. data in transfer for non ping-pong endpoint 35.5.2.4 using endpoints with ping-pong attribute the use of an endpoint with ping-pong attributes is necessary during isochronous transfer. to be able to guarantee a constant bandwidth, the microcontroller must prepare the next data pay- load to be sent while the current one is being sent by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 35-6. bank swapping data in transfer for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data in transactions: usb bus packets data in 2 data in nak ack data in 1 fifo (dpr) content load in data in 2 load in progress data in 1 cleared by firmware start to write data payload in fifo set by the firmware data payload written in fifo txcomp flag (udp_csrx) txpktrdy flag (udp_csrx) cleared by usb device pid data in data in pid pid pid pid ack pid progress prevous data in tx microcontroller load data in fifo data is sent on usb bus interrupt pending interrupt pending usb device usb bus read write read and write at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
447 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy to be cleared in the endpoint?s udp_ csrx register. 2. the microcontroller writes the first data payload to be sent in the fifo (bank 0), writing zero or more byte values in the endpoint?s udp_ fdrx register. 3. the microcontroller notifies the usb peripheral it has finished writing in bank 0 of the fifo by setting the txpktrdy in the endpoint?s udp_ csrx register. 4. without waiting for txpktrdy to be cleare d, the microcontrolle r writes the second data payload to be sent in the fifo (bank 1), writing zero or more byte values in the endpoint?s udp_ fdrx register. 5. the microcontroller is notified that the first bank has been released by the usb device when txcomp in the endpoint?s udp_ csrx re gister is set. an interrupt is pending while txcomp is being set. 6. once the microcontroller has received txco mp for the first bank, it notifies the usb device that it has prepared the second bank to be sent rising txpktrdy in the end- point?s udp_ csrx register. 7. at this step, bank 0 is available and the microcontroller can prepare a third data pay- load to be sent . figure 35-7. data in transfer for ping-pong endpoint warning: there is software critical path due to the fact that once the second bank is filled, the driver has to wait for tx_comp to set tx_pktrdy. if the delay between receiving tx_comp is set and tx_pktrdy is set is too long, some data in packets may be nacked, reducing the bandwidth. data in data in read by usb device read by usb device bank 1 bank 0 fifo (dpr) txcomp flag (udp_csrx) interrupt cleared by firmware set by usb device txpktrdy flag (udp_mcsrx) ack pid data in pid ack pid set by firmware, data payload written in fifo bank 1 cleared by usb device, data payload fully transmitted data in pid usb bus packets set by usb device set by firmware, data payload written in fifo bank 0 written by fifo (dpr) microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 usb device send bank 0 microcontroller load data in bank 0 usb device send bank 1 interrupt pending
448 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.5.2.5 data out transaction data out transactions are used in control, isochronous, bulk and interru pt transfers and con- duct the transfer of data from the host to the device. data out transactions in isochronous transfers must be done using endpoints with ping-pong attributes. 35.5.2.6 data out transaction without ping-pong attributes to perform a data out transaction, using a non ping-pong endpoint: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. while the fifo associated to this endpoint is being used by the microcontroller, a nak pid is returned to the host. once the fifo is available, data are written to the fifo by the usb device and an ack is automatically carried out to the host. 3. the microcontroller is notifie d that the usb device has re ceived a data payload polling rx_data_bk0 in the endpoint?s udp_ csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 4. the number of bytes available in the fi fo is made available by reading rxbytecnt in the endpoint?s udp_ csrx register. 5. the microcontroller carries out data received from the endpoint?s memory to its mem- ory. data received is available by reading the endpoint?s udp_ fdrx register. 6. the microcontroller notifies the usb device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s udp_ csrx register. 7. a new data out packet can be accepted by the usb device. figure 35-8. data out transfer for non ping-pong endpoints an interrupt is pending while the flag rx_dat a_bk0 is set. memory transfer between the usb device, the fifo and microcontroller memory can not be done after rx_data_bk0 has been cleared. otherwise, the usb device would acce pt the next data out transfer and overwrite the current data out packet in the fifo. ack pid data out nak pid pid pid pid pid data out2 ack data out data out 1 usb bus packets rx_data_bk0 set by usb device cleared by firmware, data payload written in fifo fifo (dpr) content written by usb device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out2 data out2 host sends the next data payload written by usb device (udp_csrx) interrupt pending
449 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.5.2.7 using endpoints with ping-pong attributes during isochronous transfer, using an endpoint with ping-pong attributes is obligatory. to be able to guarantee a constant bandwidth, the micr ocontroller must read the previous data pay- load sent by the host, while the current data payload is received by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 35-9. bank swapping in data out transfers for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data out transactions: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. it is written in the endpoint?s fifo bank 0. 3. the usb device sends an ack pid packet to the host. the host can immediately send a second data out packet. it is accepted by the device and copied to fifo bank 1. 4. the microcontroller is notifi ed that the usb device has re ceived a data payload, polling rx_data_bk0 in the endpoint?s udp_ csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 5. the number of bytes available in the fi fo is made available by reading rxbytecnt in the endpoint?s udp_ csrx register. 6. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is made available by reading the endpoint?s udp_ fdrx register. 7. the microcontroller notifies the usb peripheral device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s udp_ csrx register. 8. a third data out packet can be accepted by the usb peripheral device and copied in the fifo bank 0. 9. if a second data out packet has been received, the microcontroller is notified by the flag rx_data_bk1 set in the endpoint?s udp_ csrx register. an interrupt is pending for this endpoint while rx_data_bk1 is set. usb device usb bus read write write and read at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
450 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 10. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is available by reading the endpoint?s udp_ fdrx register. 11. the microcontroller notifies the usb device it has finished the transfer by clearing rx_data_bk1 in the endpoint?s udp_ csrx register. 12. a fourth data out packet can be accepted by the usb device and copied in the fifo bank 0. figure 35-10. data out transfer for ping-pong endpoint note: an interrupt is pending while the rx_data_bk0 or rx_data_bk1 flag is set. warning : when rx_data_bk0 and rx_data_bk1 are both set, there is no way to determine which one to clear first. thus the software must keep an internal counter to be sure to clear alter- natively rx_data_bk0 then rx_data_bk1. this situation may occur when the software application is busy elsewhere and the two banks are filled by the usb host. once the application comes back to the usb driver, the two flags are set. 35.5.2.8 status transaction a status transaction is a special type of host-to- device transaction used only in a control transfer. the control transfer must be performed using endpoints with no ping-pong attributes. according to the control sequence (read or write), the usb device sends or receives a status transaction. a p data out pid ack data out 3 data out data out 2 data out data out 1 pid data out 3 data out 1 data out1 data out 2 data out 2 pid pid pid ack cleared by firmware usb bus packets rx_data_bk0 flag rx_data_bk1 flag set by usb device, data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by usb device write in progress read by microcontroller read by microcontroller set by usb device, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data2 in bank 1, host sends third data payload cleared by firmware write by usb device fifo (dpr) (udp_csrx) (udp_csrx) interrupt pending interrupt pending
451 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 35-11. control read and write sequences notes: 1. during the status in stage, the host waits fo r a zero length packet (data in transaction with no data) from the device using data1 pid. refer to chapter 8 of the universal serial bus specifi- cation, rev. 2.0, for more information on the protocol layer. 2. during the status out stage, the host emits a zero length packet to the device (data out transaction with no data). 35.5.2.9 status in transfer once a control request has been processed, the device returns a status to the host. this is a zero length data in transaction. 1. the microcontroller waits for txpktrdy in the udp_ csrx endpoint?s register to be cleared. (at this step, txpktrdy must be cleared because the previous transaction was a setup transaction or a data out transaction.) 2. without writing anything to the udp_ fdrx endpoint?s register, the microcontroller sets txpktrdy. the usb device generates a data in packet using data1 pid. 3. this packet is acknowledged by the host and txpktrdy is set in the udp_ csrx end- point?s register. control read setup tx data out tx data out tx data stage control write setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage
452 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 35-12. data out followed by status in transfer. 35.5.2.10 status out transfer once a control request has been processed and the requested data returned, the host acknowl- edges by sending a zero length packet. this is a zero length data out transaction. 1. the usb device receives a zero length packet. it sets rx_data_bk0 flag in the udp_ csrx register and acknowledges the zero length packet. 2. the microcontroller is notified that the usb device has received a zero length packet sent by the host polling rx_data_bk0 in the udp_ csrx register. an interrupt is pending while rx_data_bk0 is set. the number of bytes received in the endpoint?s udp_ bcr register is equal to zero. 3. the microcontroller must clear rx_data_bk0. figure 35-13. data in followed by status out transfer 35.5.2.11 stall handshake a stall handshake can be used in one of two distinct occasions. (for more information on the stall handshake, refer to chapter 8 of the universal serial bus specification, rev 2.0. ) data in nak data out data out ack pid pid pid pid usb bus packets rx_data_bko (udp_csrx) cleared by firmware set by usb device cleared by usb device txpktrdy (udp_csrx) set by firmware host sends the last data payload to the device device sends a status in to the host interrupt pending data out data in data in ack pid pid pid ack pid rx_data_bko (udp_csrx) txcomp (udp_csrx) set by usb device usb bus packets cleared by firmware cleared by firmware set by usb device device sends a status out to host device sends the last data payload to host interrupt pending
453 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary a functional stall is used when the halt feature associated with the endpoint is set. (refer to chapter 9 of the universal serial bus sp ecification, rev 2.0, for more information on the halt feature.) to abort the current request, a protocol stall is used, but uniquely with control transfer. the following procedure generates a stall packet: 1. the microcontroller sets the forcestall flag in the udp_ csrx endpoint?s register. 2. the host receives the stall packet. 3. the microcontroller is notif ied that the device has sent the stall by polling the stallsent to be set. an endpoint interrup t is pending while stallsent is set. the microcontroller must clear stallsent to clear the interrupt. when a setup transaction is received after a stall handshake, stallsent must be cleared in order to prevent interrupts due to stallsent being set. figure 35-14. stall handshake (data in transfer) figure 35-15. stall handshake (data out transfer) data in stall pid pid usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device cleared by firmware interrupt pending data out pid stall pid data out usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device interrupt pending
454 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.5.3 controlling device states a usb device has several possible states. refer to chapter 9 of the universal serial bus speci- fication, rev 2.0 . figure 35-16. usb device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the us b device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 ua on the usb bus. while in suspend mode, the host may wake up a de vice by sending a resume signal (bus activ- ity) or a usb device may send a wake-up request to the host, e.g., waking up a pc by moving a usb mouse. the wake-up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
455 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.5.3.1 from powered state to default state after its connection to a usb host, the usb device waits for an end-of-bus reset. the usb host stops driving a reset state once it has detected the device?s pull-up on dp. the unmasked flag endburses is set in the register udp_isr and an interrupt is triggered. the udp software enables the default endpoint, setting the epeds flag in the udp_csr[0] register and, option- ally, enabling the interrupt for endpoint 0 by writing 1 to the udp_ier register. the enumeration then begins by a control transfer. 35.5.3.2 from default state to address state after a set address standard device request, th e usb host peripheral enters the address state. before this, it achieves the status in transaction of the control transfer, i.e., the udp device sets its new address once the txcomp flag in the udp_csr[0] register has been received and cleared. to move to address state, the driver software sets the fadden flag in the udp_glb_state, sets its new address, and sets the fen bit in the udp_faddr register. 35.5.3.3 from address state to configured state once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the epeds and eptype fields in the udp_csrx regist ers and, optionally, en abling corr esponding interrupts in the udp_ier register. 35.5.3.4 enabling suspend when a suspend (no bus activity on the usb bus) is detected, the rxsusp signal in the udp_isr register is set. this triggers an interrupt if the co rresponding bit is set in the udp_imr register. this flag is cleared by writing to the udp_icr register. then the device enters suspend mode. as an example, the microc ontroller switches to slow clock, di sables the pll and main oscillator, and goes into idle mode. it may also switch off other devices on the board. the usb device peripheral clocks may be switc hed off. however, the transceiver and the usb peripheral must not be switched off, otherwise the resume is not detected. 35.5.3.5 receiving a host resume in suspend mode, the usb transceiver and the usb peripheral must be powered to detect the resume. however, the usb device peripheral may not be clocked as the wakeup signal is asynchronous. once the resume is detected on the bus, the signal wakeup in the udp_isr is set. it may gen- erate an interrupt if the corresponding bit in the udp_imr register is set. this interrupt may be used to wake-up the core, enab le pll and main oscillators an d configure clocks. the wakeup bit must be cleared as soon as possible by setting wakeup in the udp_icr register. 35.5.3.6 sending an external resume the external resume is negotiated with the host and enabled by setting the esr bit in the udp_ glb_state. an asynchronous event on the ext_resume_pin of the peripheral generates a wakeup interrupt. on early versions of the u sp peripheral, the k-state on the usb line is generated immediately. this means that the usb device must be able to answer to the host very
456 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary quickly. on recent versions, the software sets the rmwupe bit in the udp_glb_state regis- ter once it is ready to communicate with the host. the k-state on the bus is then generated. the wakeup bit must be cleared as soon as possible by setting wakeup in the udp_icr register.
457 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6 usb device port (udp) user interface notes: 1. the addresses of the udp_ csrx registers ar e calculated as: 0x030 + 4(endpoint number - 1). 2. the addresses of the udp_ fdrx registers are calculated as: 0x050 + 4(endpoint number - 1). table 35-4. udp memory map offset register name access reset state 0x000 frame number register udp_ frm_num read 0x0000_0000 0x004 global state register udp_ glb_stat read/write 0x0000_0010 0x008 function address register udp_ faddr read/write 0x0000_0100 0x00c reserved ? ? ? 0x010 interrupt enable register udp_ ier write 0x014 interrupt disable register udp_ idr write 0x018 interrupt mask register udp_ imr read 0x0000_1200 0x01c interrupt status register udp_ isr read 0x0000_xx00 0x020 interrupt clear register udp_ icr write 0x024 reserved ? ? ? 0x028 reset endpoint register udp_ rst_ep read/write 0x02c reserved ? ? ? 0x030 endpoint 0 control and status register udp_csr0 read/write 0x0000_0000 . . . . . . see notes: (1) endpoint 5 control and status register udp_csr5 read/write 0x0000_0000 0x050 endpoint 0 fifo data register udp_ fdr0 read/write 0x0000_0000 . . . . . . see notes: (2) endpoint 5 fifo data register udp_ fdr5 read/write 0x0000_0000 0x070 reserved ? ? ? 0x074 transceiver control register udp_ txvc read/write 0x0000_0000 0x078 - 0xfc reserved ? ? ?
458 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.1 udp frame number register register name: udp_ frm_num access type: read-only frm_num[10:0]: frame number as defined in the packet field formats this 11-bit value is incremented by the host on a per fr ame basis. this value is updated at each start of frame. value updated at the sof_eop (start of frame end of packet). frm_err: frame error this bit is set at sof_eop when the sof packet is received containing an error. this bit is reset upon receipt of sof_pid. frm_ok: frame ok this bit is set at sof_eop when the sof packet is received without any error. this bit is reset upon receipt of sof_pid (packet identification). in the interrupt status register, the sof interrupt is updated upon receiving sof_pid. this bit is set without waiting for eop. note: in the 8-bit register interfac e, frm_ok is bit 4 of frm_num_h and frm_err is bit 3 of frm_num_l. 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 ??????frm_okfrm_err 15 14 13 12 11 10 9 8 ????? frm_num 76543210 frm_num
459 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.2 udp global state register register name: udp_ glb_stat access type: read/write this register is used to get and set the device state as specified in chapter 9 of the usb serial bus specification, rev.2.0 . fadden: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = no effect, only a reset can bring back a device to the default state. 1 = sets device in address state. this occurs after a succe ssful set address request. beforehand, the udp_ faddr regis- ter must have been initialized with set address parameters. set address must complete the status stage before setting fadden. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. confg: configured read: 0 = device is not in configured state. 1 = device is in configured state. write: 0 = sets device in a non configured state 1 = sets device in configured state. the device is set in configured state when it is in address st ate and receives a successful set configuration request. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. esr: enable send resume 0 = disables the remote wake up sequence. 1 = remote wake up can be processed and the pin send_resume is enabled. rsminpr: a resume has been sent to the host read: 0 = no effect. 1 = a resume has been received from the host during remote wake up feature. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ? ? ? rmwupe rsminpr esr confg fadden
460 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary rmwupe: remote wake up enable 0 = must be cleared after receiving any host packet or sof interrupt. 1 = enables the k-state on the usb cable if esr is enabled.
461 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.3 udp function address register register name: udp_ faddr access type: read/write fadd[6:0]: function address value the function address value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. refer to the universal serial bus specification, rev. 2.0 for more information. after power up or reset, the function address value is set to 0. fen: function enable read: 0 = function endpoint disabled. 1 = function endpoint enabled. write: 0 = disables function endpoint. 1 = default value. the function enable bit (fen) allows the microcontroller to enable or disable the function endpoints. the microcontroller sets this bit after receipt of a reset from the host. once this bit is set, the usb device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?fen 76543210 ?fadd
462 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.4 udp interrupt enable register register name: udp_ ier access type: write-only ep0int: enable endpoint 0 interrupt ep1int: enable endpoint 1 interrupt ep2int: enable endpoint 2interrupt ep3int: enable endpoint 3 interrupt ep4int: enable endpoint 4 interrupt ep5int: enable endpoint 5 interrupt 0 = no effect. 1 = enables corresponding endpoint interrupt. rxsusp: enable udp suspend interrupt 0 = no effect. 1 = enables udp suspend interrupt. rxrsm: enable udp resume interrupt 0 = no effect. 1 = enables udp resume interrupt. extrsm: enable external resume interrupt 0 = no effect. 1 = enables external resume interrupt. sofint: enable start of frame interrupt 0 = no effect. 1 = enables start of frame interrupt. wakeup: enable udp bus wakeup interrupt 0 = no effect. 1 = enables usb bus interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int
463 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.5 udp interrupt disable register register name: udp_ idr access type: write-only ep0int: disable endpoint 0 interrupt ep1int: disable endpoint 1 interrupt ep2int: disable endpoint 2 interrupt ep3int: disable endpoint 3 interrupt ep4int: disable endpoint 4 interrupt ep5int: disable endpoint 5 interrupt 0 = no effect. 1 = disables corresponding endpoint interrupt. rxsusp: disable udp suspend interrupt 0 = no effect. 1 = disables udp suspend interrupt. rxrsm: disable udp resume interrupt 0 = no effect. 1 = disables udp resume interrupt. extrsm: disable external resume interrupt 0 = no effect. 1 = disables external resume interrupt. sofint: disable start of frame interrupt 0 = no effect. 1 = disables start of frame interrupt wakeup: disable usb bus interrupt 0 = no effect. 1 = disables usb bus wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int
464 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.6 udp interrupt mask register register name: udp_ imr access type: read-only ep0int: mask endpoint 0 interrupt ep1int: mask endpoint 1 interrupt ep2int: mask endpoint 2 interrupt ep3int: mask endpoint 3 interrupt ep4int: mask endpoint 4 interrupt ep5int: mask endpoint 5 interrupt 0 = corresponding endpoint interrupt is disabled. 1 = corresponding endpoint interrupt is enabled. rxsusp: mask udp suspend interrupt 0 = udp suspend interrupt is disabled. 1 = udp suspend interrupt is enabled. rxrsm: mask udp resume interrupt. 0 = udp resume interrupt is disabled. 1 = udp resume interrupt is enabled. extrsm: mask external resume interrupt 0 = external resume interrupt is disabled. 1 = external resume interrupt is enabled. sofint: mask start of frame interrupt 0 = start of frame interrupt is disabled. 1 = start of frame interrupt is enabled. wakeup: usb bus wakeup interrupt 0 = usb bus wakeup interrupt is disabled. 1 = usb bus wakeup interrupt is enabled. note: when the usb block is in suspend mode, the application may po wer down the usb logic. in this case, any usb host resume request that is made must be taken into account and, thus, the reset value of th e rxrsm bit of the register udp_ imr is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int
465 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.7 udp interrupt status register register name: udp_ isr access type: read-only ep0int: endpoint 0 interrupt status 0 = no endpoint0 interrupt pending. 1 = endpoint0 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr0: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep0int is a sticky bit. interrupt remains valid until ep0int is cleared by writing in the corresponding udp_ csr0 bit. ep1int: endpoint 1 interrupt status 0 = no endpoint1 interrupt pending. 1 = endpoint1 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr1: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep1int is a sticky bit. interrupt remains valid until ep1int is cleared by writing in the corresponding udp_ csr1 bit. ep2int: endpoint 2 interrupt status 0 = no endpoint2 interrupt pending. 1 = endpoint2 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr2: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusre s sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int
466 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary txcomp set to 1 stallsent set to 1 ep2int is a sticky bit. interrupt remains valid until ep2int is cleared by writing in the corresponding udp_ csr2 bit. ep3int: endpoint 3 interrupt status 0 = no endpoint3 interrupt pending. 1 = endpoint3 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr3: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep3int is a sticky bit. interrupt remains valid until ep3int is cleared by writing in the corresponding udp_ csr3 bit. ep4int: endpoint 4 interrupt status 0 = no endpoint4 interrupt pending. 1 = endpoint4 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr4: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep4int is a sticky bit. interrupt remains valid until ep4int is cleared by writing in the corresponding udp_ csr4 bit. ep5int: endpoint 5 interrupt status 0 = no endpoint5 interrupt pending. 1 = endpoint5 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr5: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep5int is a sticky bit. interrupt remains valid until ep5int is cleared by writing in the corresponding udp_ csr5 bit. rxsusp: udp suspend interrupt status 0 = no udp suspend interrupt pending. 1 = udp suspend interrupt has been raised. the usb device sets this bit when it detects no ac tivity for 3ms. the usb device enters suspend mode. rxrsm: udp resume interrupt status 0 = no udp resume interrupt pending. 1 =udp resume interrupt has been raised.
467 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the usb device sets this bit when a udp resume signal is detected at its port. after reset, the state of this bit is undefined, the application mu st clear this bit by setting the rxrsm flag in the udp_ icr register. extrsm: external re sume interrupt status 0 = no external resume interrupt pending. 1 = external resume interrupt has been raised. this interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. if rmwupe = 1, a resume state is sent in the usb bus. sofint: start of frame interrupt status 0 = no start of frame interrupt pending. 1 = start of frame interrupt has been raised. this interrupt is raised each time a sof token has been detected. it can be used as a synchronization signal by using isochronous endpoints. endbusres: end of bus reset interrupt status 0 = no end of bus reset interrupt pending. 1 = end of bus reset interrupt has been raised. this interrupt is raised at the end of a udp reset sequence. the usb device must prepare to receive requests on the end- point 0. the host starts the enumeration, then performs the configuration. wakeup: udp resume interrupt status 0 = no wakeup interrupt pending. 1 = a wakeup interrupt (usb host sent a resume or reset) occurred since the last clear. after reset the state of this bit is undefined, the applic ation must clear this bit by sett ing the wakeup flag in the udp_ icr register.
468 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.8 udp interrupt clear register register name: udp_ icr access type: write-only rxsusp: clear udp suspend interrupt 0 = no effect. 1 = clears udp suspend interrupt. rxrsm: clear udp resume interrupt 0 = no effect. 1 = clears udp resume interrupt. extrsm: clear external resume interrupt 0 = no effect. 1 = clears external resume interrupt. sofint: clear start of frame interrupt 0 = no effect. 1 = clears start of frame interrupt. endburses: clear end of bus reset interrupt 0 = no effect. 1 = clears end of bus reset interrupt. wakeup: clear wakeup interrupt 0 = no effect. 1 = clears wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endburses sofint extrsm rxrsm rxsusp 76543210 ????????
469 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.9 udp reset en dpoint register register name: udp_ rst_ep access type: read/write ep0: reset endpoint 0 ep1: reset endpoint 1 ep2: reset endpoint 2 ep3: reset endpoint 3 ep4: reset endpoint 4 ep5: reset endpoint 5 this flag is used to reset the fifo associated with the en dpoint and the bit rxbytecount in the register udp_csrx.it also resets the data toggle to data0. it is useful after removing a halt cond ition on a bulk endpoint. refer to chapter 5.8.5 in the usb serial bus specification, rev.2.0 . warning: this flag must be cleared at the end of the reset. it does not clear udp_ csrx flags. 0 = no reset. 1 = forces the corresponding end point fif0 pointers to 0, ther efore rxbytecnt field is read at 0 in udp_ csrx register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ? ? ep5 ep4 ep3 ep2 ep1 ep0
470 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.10 udp endpoint control and status register register name: udp_ csrx [x = 0..5] access type: read/write txcomp: generates an in packet with data previously written in the dpr this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = clear the flag, clear the interrupt. 1 = no effect. read (set by the usb peripheral): 0 = data in transaction has not been acknowledged by the host. 1 = data in transaction is achieved, acknowledged by the host. after having issued a data in transaction setting txpktrdy, the device firmware waits for txcomp to be sure that the host has acknowledged the transaction. rx_data_bk0: receive data bank 0 this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notify usb peripheral device that data have been read in the fifo's bank 0. 1 = no effect. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 0 1 = a data packet has been received, it has been stored in the fifo's bank 0. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to the microcontroller memory. the number of bytes received is available in rxbytcent field. bank 0 fifo values are read through the udp_ fdrx register. once a transfer is done, the device firmware must release bank 0 to the usb peripheral device by clearing rx_data_bk0. 31 30 29 28 27 26 25 24 ????? r xbytecnt 23 22 21 20 19 18 17 16 rxbytecnt 15 14 13 12 11 10 9 8 epeds ? ? ? dtgle eptype 76543210 dir rx_data_ bk1 force stall txpktrdy stallsent isoerror rxsetup rx_data_ bk0 txcomp
471 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary rxsetup: sends stall to the host (control endpoints) this flag generates an interr upt while it is set to one. read: 0 = no setup packet available. 1 = a setup data packet has been sent by the host and is available in the fifo. write: 0 = device firmware notifies the usb peripheral device that it has read the setup data in the fifo. 1 = no effect. this flag is used to notify the usb device firmware that a valid setup data packet has been sent by the host and success- fully received by the usb device. the usb device firmware ma y transfer setup data from the fifo by reading the udp_ fdrx register to the mi crocontroller memory. once a tr ansfer has been done, rxsetup mu st be cleared by the device firmware. ensuing data out transaction is not accepted while rxsetup is set. stallsent: stall sent (control, bulk interrupt endpoints) / isoerror (isochronous endpoints) this flag generates an interr upt while it is set to one. stallsent: this ends a stall handshake. read: 0 = the host has not acknowledged a stall. 1 = host has acknowledged the stall. write: 0 = resets the stallsent flag, clears the interrupt. 1 = no effect. this is mandatory for the device firmware to clear this flag. otherwise the interrupt remains. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. isoerror: a crc error has been detected in an isochronous transfer. read: 0 = no error in the prev ious isochronous transfer. 1 = crc error has been detected, data available in the fifo are corrupted. write: 0 = resets the isoerror flag, clears the interrupt. 1 = no effect. txpktrdy: transmit packet ready this flag is cleared by the usb device. this flag is set by the usb device firmware. read: 0 = data values can be written in the fifo. 1 = data values can not be written in the fifo.
472 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary write: 0 = no effect. 1 = a new data payload is has been written in the fifo by the firmware and is ready to be sent. this flag is used to generate a data in transaction (device to host). device firmware checks that it can write a data payload in the fifo, checking that txpktrdy is clear ed. transfer to the fifo is done by writing in the udp_ fdrx register. once the data payload has been transferred to the fifo, the firmwar e notifies the usb device setting txpktrdy to one. usb bus transactions can start. txcomp is set once the data payload has been received by the host. forcestall: force stall (used by control, bulk and isochronous endpoints) write-only 0 = no effect. 1 = sends stall to the host. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. control endpoints: during the data stage and status stage, this indicates that the microcontroller cannot complete the request. bulk and interrupt endpoints: notifies the host that the endpoint is halted. the host acknowledges the stall, device fi rmware is notified by the stallsent flag. rx_data_bk1: receive data bank 1 (only used by endpoints with ping-pong attributes) this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notifies usb device that data have been read in the fifo?s bank 1. 1 = no effect. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 1. 1 = a data packet has been received, it has been stored in fifo's bank 1. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to microcontroller memory. the number of bytes received is available in rxbytecnt field. bank 1 fifo values are read through udp_ fdrx register. once a transfer is done, the de vice firmware must release bank 1 to the usb device by clearing rx_data_bk1. dir: transfer direction (only available for control endpoints) read/write 0 = allows data out transactio ns in the control data stage. 1 = enables data in transactions in the control data stage. refer to chapter 8.5.3 of the universal serial bus specification, rev. 2.0 for more information on the control data stage. this bit must be set before udp_ csrx/r xsetup is cleared at the end of the setu p stage. according to the request sent in the setup data packet, the data stage is either a device to host (dir = 1) or host to device (dir = 0) data transfer. it is not necessary to check this bit to reve rse direction for the status stage.
473 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary eptype[2:0]: endpoint type dtgle: data toggle read-only 0 = identifies data0 packet. 1 = identifies data1 packet. refer to chapter 8 of the universal serial bus specification, rev. 2.0 for more information on data0, data1 packet definitions. epeds: endpoint enable disable read: 0 = endpoint disabled. 1 = endpoint enabled. write: 0 = disables endpoint. 1 = enables endpoint. rxbytecnt[10:0]: number of bytes available in the fifo read-only when the host sends a data packet to the device, the usb device stores the data in the fifo and notifies the microcontrol- ler. the microcontroller can lo ad the data from t he fifo by reading rxbytecent byte s in the udp_ fdrx register. read/write 000 control 001 isochronous out 101 isochronous in 010 bulk out 110 bulk in 011 interrupt out 111 interrupt in
474 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.6.11 udp fifo data register register name: udp_ fdrx [x = 0..5] access type: read/write fifo_data[7:0]: fifo data value the microcontroller can push or pop values in the fifo through this register. rxbytecnt in the corresponding udp_ csrx register is the num ber of bytes to be read from the fifo (sent by the host). the maximum number of bytes to write is fixed by the max packet size in the standard endpoint descriptor. it can not be more than the physical memory size associated to the endpoint. refer to the universal serial bus specification, rev. 2.0 for more information. 35.6.12 udp transceiver control register register name: udp_ txvc access type: read/write txvdis: transceiver disable when udp is disabled, power consumption can be reduced significantly by disab ling the embedded transceiver. this can be done by setting txvdis field. to enable the transceiver, txvdis must be cleared. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 fifo_data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? txvdis 76543210 ?????? ??
475 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36. analog-to-digital converter (adc) 36.1 overview the adc is based on a successive approximatio n register (sar) 10-bit analog-to-digital con- verter (adc). it also integrates an 8-to-1 analog multiplexer, making possible the analog-to- digital conversions of up to eight analog lines. the conversions extend from 0v to advref. the adc supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. software trigger, external trigger on rising edge of the adtrg pin or internal triggers from timer counter out- put(s) are configurable. the adc also integrates a sleep mode and a conversion sequencer and connects with a pdc channel. these features reduce both power consumption and processor intervention. finally, the user can configure adc timings, such as startup time and sample & hold time. 36.2 block diagram figure 36-1. analog-to-digital conv erter block diagram adc interrupt adc adtrg ad0 vddin advref gnd ad1 ad2 ad3 trigger selection control logic successive approximation register analog-to-digital converter timer counter channels user interface aic peripheral bridge apb pdc asb ad4 ad5 ad6 ad7 pio
476 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.3 signal description 36.4 product dependencies 36.4.1 power management the adc is automatically clocked after the first conversion in normal mode. in sleep mode, the adc clock is automatically stopped after each conversion. as the logic is small and the adc cell can be put into sleep mode, the power management controller has no effect on the adc behavior. 36.4.2 interrupt sources the adc interrupt line is connected on one of th e internal sources of the advanced interrupt controller. using the adc interrupt requires the aic to be programmed first. 36.4.3 analog inputs the pins ad0 to ad7 can be multiplexed with pio lines. in this case, the assignment of the adc input is automatically done as soon as the corresponding channel is enabled by writing the reg- ister adc_cher. by default, after reset, the pio line is configured as input with its pull-up enabled and the adc input is connected to the gnd. 36.4.4 i/o lines the pin adtrg may be shared with other peripheral functions through the pio controller. in this case, the pio controller should be set acco rdingly to assign the pin adtrg to the adc function. 36.4.5 timer triggers timer counters may or may not be used as hardware triggers depending on user requirements. thus, some or all of the timer counters may be non-connected. 36.4.6 conversion performances for performance and electrical c haracteristics of the adc, see section 41.7 ?adc characteris- tics?, on page 642 . table 36-1. adc pin description pin name description vddin analog power supply advref reference voltage ad0 - ad 7 analog input channels adtrg external trigger
477 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.5 functional description 36.5.1 analog-to-digital conversion the adc uses the adc clock to perform conversi ons. converting a single analog value to a 10- bit digital data requires sample and hold clock cycles as defined in the field shtim of the ?adc mode register? on page 483 and 10 adc clock cycles. the adc clock frequency is selected in the prescal field of the mode register (adc_mr). the adc clock range is between mck/2, if prescal is 0, and mck/128, if prescal is set to 63 (0x3f). prescal must be programmed in order to provide an adc clock frequency accord- ing to the parameters given in the product definition section. 36.5.2 conversion reference the conversion is performed on a full range be tween 0v and the reference voltage pin advref. analog inputs between these voltages convert to values based on a linear conversion. 36.5.3 conversion resolution the adc supports 8-bit or 10-bit resolutions. the 8- bit selection is performed by setting the bit lowres in the adc mode register (adc_mr). by default, after a reset, the resolution is the highest and the data field in the data registers is fully used. by setting the bit lowres, the adc switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. the two hi ghest bits of the data field in the corresponding adc_cdr register and of the ldata field in the adc_lcdr register read 0. moreover, when a pdc channel is connected to the adc, 10-bit resolution sets the transfer request sizes to 16-bit. setting the bit lowres autom atically switches to 8-bit data transfers. in this case, the destination buffers are optimized. 36.5.4 conversion results when a conversion is completed, the resulting 10-bit digital value is stored in the channel data register (adc_cdr) of the current channel and in the adc last converted data register (adc_lcdr). the channel eoc bit in the status register (adc_sr) is set and th e drdy is set. in the case of a connected pdc channel, drdy rising triggers a data transfer request. in any case, either eoc and drdy can trigger an interrupt. reading one of the adc_cdr registers clears the corresponding eoc bit. reading adc_lcdr clears the drdy bit and the eoc bit corresponding to the last converted channel.
478 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 36-2. eocx and drdy flag behavior if the adc_cdr is not read befo re further incoming data is converted, the corresponding over- run error (ovre) flag is set in the status register (adc_sr). in the same way, new data converted when drdy is high sets the bit govre (general overrun error) in adc_sr. the ovre and govre flags are automatically cleared when adc_sr is read. conversion time read the adc_cdrx eocx drdy read the adc_lcdr chx (adc_chsr) (adc_sr) (adc_sr) write the adc_cr with start = 1 conversion time write the adc_cr with start = 1
479 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 36-3. govre and ovrex flag behavior warning: if the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 36.5.5 conversion triggers conversions of the active analog channels are started with a software or a hardware trigger. the software trigger is provided by writing the control register (adc_ cr) with the bit start at 1. the hardware trigger can be one of the tioa outputs of the timer counter channels, or the external trigger input of the adc (adtrg). the hardware trigger is selected with the field trg- sel in the mode register (adc_mr). the selected hardware trigger is enabled with the bit trgen in the mode register (adc_mr). if a hardware trigger is selected, the start of a c onversion is detected at each rising edge of the selected signal. if one of the tioa outputs is selected, the corresponding timer counter channel must be programmed in waveform mode. only one start command is necessary to initiate a conversion sequence on all the channels. the adc hardware logic automatically performs the conversions on the active channels, then waits eoc0 govre ch0 (adc_chsr) (adc_sr) (adc_sr) adtrg eoc1 ch1 (adc_chsr) (adc_sr) ovre0 (adc_sr) undefined data data a data b adc_lcdr undefined data data a adc_cdr0 undefined data data b adc_cdr1 data c data c conversion conversion read adc_sr drdy (adc_sr) read adc_cdr1 read adc_cdr0 conversion
480 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary for a new request. the channel enable (adc_cher) and channel disable (adc_chdr) reg- isters enable the analog channels to be enabled or disabled independently. if the adc is used with a pdc, only the transfe rs of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. warning: enabling hardware triggers does not disable the software trigger functionality. thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 36.5.6 sleep mode and conversion sequencer the adc sleep mode maximizes power saving by aut omatically deactivating the adc when it is not being used for conversions. sleep mode is se lected by setting the bit sleep in the mode register adc_mr. the sleep mode is automatically managed by a conversion sequencer, which can automati- cally process the conversions of all channels at lowest power consumption. when a start conversion request occurs, the adc is automatically activated. as the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. when all conversions are complete, the adc is deactivated until the next trigger. trig- gers occurring during the sequence are not taken into account. the conversion sequencer allows automatic pr ocessing with minimum processor intervention and optimized power consumption. conversion sequences can be performed periodically using a timer/counter output. the periodic acquisition of several samples can be processed automat- ically without any intervention of the processor thanks to the pdc. note: the reference voltage pins always remain connected in normal mode as in sleep mode. 36.5.7 adc timings each adc has its own minimal startup time that is programmed through the field startup in the mode register adc_mr. in the same way, a minimal sample and hold time is necessary for the adc to guarantee the best converted final value between two channels selection. this time has to be programmed through the bitfield shtim in the mode register adc_mr. warning: no input buffer amplifier to isolate the source is included in the adc. this must be taken into consideration to program a precise value in the shtim field. see the section dc characteristics in the product datasheet.
481 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6 analog-to-digital con verter (adc) user interface table 36-2. analog-to-digital converte r (adc) register mapping offset register name access reset state 0x00 control register adc_cr write-only ? 0x04 mode register adc_mr read/write 0x00000000 0x08 reserved ? ? ? 0x0c reserved ? ? ? 0x10 channel enable register adc_cher write-only ? 0x14 channel disable register adc_chdr write-only ? 0x18 channel status register adc_chsr read-only 0x00000000 0x1c status register adc_sr read-only 0x000c0000 0x20 last converted data register adc_lcdr read-only 0x00000000 0x24 interrupt enable register adc_ier write-only ? 0x28 interrupt disable register adc_idr write-only ? 0x2c interrupt mask register adc_imr read-only 0x00000000 0x30 channel data register 0 adc_cdr0 read-only 0x00000000 0x34 channel data register 1 adc_cdr1 read-only 0x00000000 0x38 channel data register 2 adc_cdr2 read-only 0x00000000 0x3c channel data register 3 adc_cdr3 read-only 0x00000000 0x40 channel data register 4 adc_cdr4 read-only 0x00000000 0x44 channel data register 5 adc_cdr5 read-only 0x00000000 0x48 channel data register 6 adc_cdr6 read-only 0x00000000 0x4c channel data register 7 adc_cdr7 read-only 0x00000000 0x50 - 0xfc reserved ? ? ?
482 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.1 adc control register register name: adc_cr access type: write-only swrst: software reset 0 = no effect. 1 = resets the adc simulating a hardware reset. start: start conversion 0 = no effect. 1 = begins analog-to-digital conversion. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? start swrst
483 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.2 adc mode register register name: adc_mr access type: read/write trgen: trigger enable trgsel: trigger selection lowres: resolution sleep: sleep mode 31 30 29 28 27 26 25 24 ???? shtim 23 22 21 20 19 18 17 16 ? ? ? startup 15 14 13 12 11 10 9 8 ?? prescal 76543210 ? ? sleep lowres trgsel trgen trgen selected trgen 0 hardware triggers are disabled. starting a conversion is only possible by software. 1 hardware trigger selected by trgsel field is enabled. trgsel selected trgsel 0 0 0 tioa ouput of the timer counter channel 0 0 0 1 tioa ouput of the timer counter channel 1 0 1 0 tioa ouput of the timer counter channel 2 (reserved on at91sam7s32) 011reserved 100reserved 101reserved 1 1 0 external trigger 111reserved lowres selected resolution 0 10-bit resolution 1 8-bit resolution sleep selected mode 0 normal mode 1 sleep mode
484 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary prescal: prescaler rate selection adcclock = mck / ( (prescal+1) * 2 ) startup: start up time startup time = (startup+1) * 8 / adcclock shtim: sample & hold time sample & hold time = (shtim+1) / adcclock
485 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.3 adc channel enable register register name: adc_cher access type: write-only chx: channel x enable 0 = no effect. 1 = enables the corresponding channel. 36.6.4 adc channel disable register register name: adc_chdr access type: write-only chx: channel x disable 0 = no effect. 1 = disables the corresponding channel. warning: if the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver- sion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
486 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.5 adc channel status register register name: adc_chsr access type: read-only chx: channel x status 0 = corresponding c hannel is disabled. 1 = corresponding channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
487 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.6 adc status register register name: adc_sr access type: read-only eocx: end of conversion x 0 = corresponding analog channel is disabl ed, or the conversion is not finished. 1 = corresponding analog channel is enabled and conversion is complete. ovrex: overrun error x 0 = no overrun error on the corresponding channel since the last read of adc_sr. 1 = there has been an overrun error on the corres ponding channel since the last read of adc_sr. drdy: data ready 0 = no data has been converted since the last read of adc_lcdr. 1 = at least one data has been conv erted and is ava ilable in adc_lcdr. govre: general overrun error 0 = no general overrun error occurred since the last read of adc_sr. 1 = at least one general overrun error has occurred since the last read of adc_sr. endrx: end of rx buffer 0 = the receive counter register has not reach ed 0 since the last write in adc_rcr or adc_rncr. 1 = the receive counter register has reached 0 since the last write in adc_rcr or adc_rncr. rxbuff: rx buffer full 0 = adc_rcr or adc_rncr ha ve a value other than 0. 1 = both adc_rcr and adc_rncr have a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
488 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.7 adc last conv erted data register register name: adc_lcdr access type: read-only ldata: last data converted the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. 36.6.8 adc interrupt enable register register name: adc_ier access type: write-only eocx: end of conversion interrupt enable x ovrex: overrun error interrupt enable x drdy: data ready interrupt enable govre: general overrun error interrupt enable endrx: end of receive buffer interrupt enable rxbuff: receive buffer full interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ldata 76543210 ldata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
489 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.9 adc interrupt disable register register name: adc_idr access type: write-only eocx: end of conversion interrupt disable x ovrex: overrun error interrupt disable x drdy: data ready interrupt disable govre: general overrun error interrupt disable endrx: end of receive buffer interrupt disable rxbuff: receive buffer full interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
490 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 36.6.10 adc interrupt mask register register name: adc_imr access type: read-only eocx: end of conversion interrupt mask x ovrex: overrun erro r interrupt mask x drdy: data ready interrupt mask govre: general overrun error interrupt mask endrx: end of receive buffer interrupt mask rxbuff: receive buffer full interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 36.6.11 adc channe l data register register name: adc_cdrx access type: read-only data: converted data the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. the convert data re gister (cdr) is only loaded if the co rresponding analog channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? data 76543210 data
491 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37. advanced encryption standard (aes) 37.1 overview the advanced encryption standard (aes) is compliant with the american fips (federal infor- mation processing standard) publication 197 specification. the aes supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ecb, cbc, ofb, cfb and ctr), as specified in the nist special publication 800- 38a recommendation. it is compatible with all these modes via peripheral dma controller chan- nels, minimizing processor intervention for large buffer transfers. the 128-bit key and input data (and initialization vector for some modes) are each stored in four 32-bit registers (aes_keywxr, aes_idatax r and aes_ivxr) which are all write-only. as soon as the initialization vector, the input data and the key are configured, the encryp- tion/decryption process may be started. then the encrypted/decrypted data is ready to be read out on the four 32-bit output data registers (aes_odataxr) or through the pdc channels. 37.2 product dependencies 37.2.1 power management the aes may be clocked through the power manage ment controller (pmc), so the programmer must first to configure the pmc to enable the aes clock. 37.2.2 interrupt the aes interface has an interrupt line connecte d to the advanced interrupt controller (aic). handling the aes interrupt requires programming the aic before configuring the aes.
492 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.3 functional description the advanced encryption standard (aes) specif ies a fips-approved cryptographic algorithm that can be used to protect electronic data. the aes algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. encryption converts data to an unintelligible form called ciphertext. decrypting the ciphertext converts the data back into its original form, called plaintext. the cipher bit in the aes mode register (aes_mr) allows sele ction between the encryption and the decryption processes. the aes is capable of using cryptographic keys of 128 bits to encrypt and decrypt data in blocks of 128 bits. this 128-bit key is de fined in the key registers (aes_keywxr). the input to the encryption processes of the cbc, cfb, and ofb modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector (iv), which must be set in the ini- tialization vector registers (aes_ivxr). the initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. the initialization vector registers are also used by the ctr mode to set the counter value. 37.3.1 operation modes the aes supports the following modes of operation: ecb: electronic code book cbc: cipher block chaining ofb: output feedback cfb: cipher feedback ? cfb8 (cfb where the length of the data segment is 8 bits) ? cfb16 (cfb where the length of the data segment is 16 bits) ? cfb32 (cfb where the length of the data segment is 32 bits) ? cfb64 (cfb where the length of the data segment is 64 bits) ? cfb128 (cfb where the length of the data segment is 128 bits) ctr: counter the data pre-processing, post-processing and data chaining for the concerned modes are auto- matically performed. refer to the nist special publication 800-38a recommendation for more complete information. these modes are selected by setting the opmod field in th e aes mode register (aes_mr). in cfb mode, five data sizes are possible (8, 16, 32, 64 or 128 bits), configurable by means of the cfbs field in the mode register. ( see ?aes mode register? on page 500. ). 37.3.2 start modes the smod field in the aes mode register (aes_ mr) allows selection of the encryption (or decryption) start mode. 37.3.2.1 manual mode the sequence is as follows: write the 128-bit key in the key registers (aes_keywxr).
493 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary write the initialization vector (or counter) in the initialization vector registers (aes_ivxr). note: the initialization vector registers concern all modes except ecb. set the bit datrdy (data ready) in the aes interrupt enable register (aes_ier), depending on whether an interrupt is required or not at the end of processing. write the data to be encrypted/decrypted in the authorized input data registers (see table 37-1 ). note: in 64-bit cfb mode, writing to aes_idata3r and aes_idata4r registers is not allowed and may lead to errors in processing. note: in 32-, 16- and 8-bit cf b modes, writing to aes_idata2r, aes_idata3r and aes_idata4r registers is not allowed and may lead to errors in processing. set the start bit in the aes control regist er aes_cr to begin th e encryption or the decryption process. when processing completes, the bit datr dy in the aes interrupt status register (aes_isr) raises. if an interrupt has been en abled by setting the bit datrdy in aes_ier, the interrupt line of the aes is activated. when the software reads one of the output data registers (aes_odataxr), the datrdy bit is automatically cleared. 37.3.2.2 auto mode the auto mode is similar to the manual one, except that in this mode, as soon as the correct number of input data registers is written, processing is automatically started without any action in the control register. 37.3.2.3 pdc mode the peripheral dma controller (pdc) can be used in association with the aes to perform an encryption/decryption of a buffer without any action by the software during processing. table 37-1. authorized input data registers operation mode input data registers to write ecb all cbc all ofb all 128-bit cfb all 64-bit cfb aes_idata1r and aes_idata2r 32-bit cfb aes_idata1r 16-bit cfb aes_idata1r 8-bit cfb aes_idata1r ctr all
494 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary in this starting mode, the type of the data transfer (byte, half-word or word) depends on the oper- ation mode. the sequence is as follows: write the 128-bit key in the key registers (aes_keywxr). write the initialization vector (or counter) in the initialization vector registers (aes_ivxr). note: the initialization vector registers concern all modes except ecb. set the transmit pointer register (aes_tpr) to the address where the data buffer to encrypt/decrypt is stored and the receive pointer register (aes_rpr) where it must be encrypted/decrypted. note: transmit and receive buffers can be identical. set the transmit and the receive counter registers (aes_tcr and aes_rcr) to the same value. this value must be a multiple of the data transfer type size (see table 37-2 ). note: the same requirements are necessary for the next pointer(s) and counter(s) of the pdc (aes_tnpr, aes_rnpr, aes_tncr, aes_rncr). if not already done, set the bit endrx (or rx buff if the next point ers and counters are used) in the aes interrupt enable register (aes_ier), depending on whether an interrupt is required or not at the end of processing. enable the pdc in transmissi on and reception to start the processing (aes_ptcr). when the processing completes, the bit endrx (or rxbuff) in the aes interrupt status register (aes_isr) raises. if an interrupt ha s been enabled by setti ng the corresponding bit in aes_ier, the interrupt lin e of the aes is activated. 37.3.3 last output data mode this mode is used to generate cryptographi c checksums on data (mac ) by means of cipher block chaining encryption algorithm (cbc-mac algorithm for example). after each end of encryption/decryption, the output data is available either on the output data registers for manual and auto mode or at the address specified in the receive buffer pointer for pdc mode (see table on page 496 ). the last output data bit (lod) in the aes mode register (aes_mr) allows retrieva l of only the last data of several encryption/decryption processes. table 37-2. data transfer type for the different operation modes operation mode data transfer type (pdc) ecb word cbc word ofb word cfb 128-bit word cfb 64-bit word cfb 32-bit word cfb 16-bit half-word cfb 8-bit byte ctr word
495 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary therefore, there is no need to define a read buffer in pdc mode. this data is only ava ilable on the output data registers (aes_odataxr). 37.3.3.1 manual and auto modes if lod = 0 the datrdy flag is cleared when at least one of the output data registers is read (see figure 37-1 ). figure 37-1. manual and auto modes with lod = 0 if the user does not want to read the output data registers between each encryption/decryption, the datrdy flag will not be clear ed. if the datrdy flag is not cleared, the user cannot know the end of the following encryptions/decryptions. if lod = 1 the datrdy flag is cleared when at least one inpu t data register is written, so before the start of a new transfer (see figure 37-2 ). no more output data register reads are necessary between consecutive encryptions/decryptions. figure 37-2. manual and auto modes with lod = 1 37.3.3.2 pdc mode if lod = 0 the end of the encryption/decryption is notified by the endrx (or rxbuff) flag rise (see figure 37-3 ). encryption or decryption process read the aes_odataxr write start bit in aes_cr (manual mode) datrdy write aes_idataxr register(s) (auto mode) or write aes_idataxr register(s) write start bit in aes_cr (manual mode) write aes_idataxr register(s) (auto mode) or encryption or decryption process datrdy
496 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 37-3. pdc mode with lod = 0 if lod = 1 the user must first wait for the endtx (or txbufe) flag to rise, then for datrdy to ensure that the encryption/decryption is completed (see figure 37-4 ). in this case, no receive buffers are required. the output data is only available on the output data registers (aes_odataxr). figure 37-4. pdc mode with lod = 1 table 37-3 summarizes the different cases. note: 1. depending on the mode, there are other ways of clearing the datrdy flag. see ?aes interrupt status register? on page 505 . warning: in pdc mode, reading to the output data registers before the last data transfer may lead to unpredictable results. enable pdc channels (receive and transmit channels) multiple encryption or decryption processes endrx (or rxbuff) enable pdc channels (only transmit channels) multiple encryption or decryption processes datrdy endtx (or txbufe) table 37-3. last output mode behavior versus start modes manual and auto modes pdc mode lod = 0 lod = 1 lod = 0 lod = 1 datrdy flag clearing condition (1) at least one output data register must be read at least one input data register must be written not used managed by the pdc encrypted/decrypted data result location in the output data registers in the output data registers at the address specified in the receive pointer register (aes_rpr) in the output data registers end of encryption/ decryption datrdy datrdy endrx (or rxbuff) endtx (or txbufe) then datrdy
497 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.3.4 security features 37.3.4.1 countermeasures the aes also features hardware c ountermeasures that c an be useful to protect data against dif- ferential power analysis (dpa) attacks. these countermeasures can be enabled through the ctype field in the aes mode register. this field is write-only, and all changes to it are taken into account if, at the same time, the coun- termeasure key (ckey field) is correc tly written (see ?aes mode regist er? on page 500 ). note: enabling countermeasures has an impact on the aes encryption/decryption throughput. by default, all the countermeasures are enabled. the best throughput is achieved with all the c ountermeasures disabled. on the other hand, the best protection is achieved with all of them enabled. the loadseed bit in the aes control register (aes_cr) allows a new seed to be loaded in the embedded random number generator used for the different countermeasures. 37.3.4.2 unspecified register access detection when an unspecified register ac cess occurs, the urad bit in th e interrupt status register (aes_isr) raises. its source is then reported in th e unspecified register access type field (urat). only the last unspecified register access is available through the urat field. several kinds of unspecified register accesses can occur: input data register written during the data processing in pdc mode output data register read during data processing mode register written during data processing output data register read during sub-keys generation mode register written during sub-keys generation write-only register read access the urad bit and the urat field can only be reset by the swrst bi t in the aes_cr control register.
498 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4 advanced encryption standar d (aes) user interface table 37-4. aes 128-bit register mapping offset register register name read/write reset 0x00 control register aes_cr write-only ? 0x04 mode register aes_mr read/write 0x0 0x08-0x0c reserved ??? 0x10 interrupt enable register aes_ier write-only ? 0x14 interrupt disable r egister aes_idr write-only ? 0x18 interrupt mask register aes_imr read-only 0x0 0x1c interrupt status register aes_isr read-only 0x0000001e 0x20 key word 1 register aes_keyw1r write-only ? 0x24 key word 2 register aes_keyw2r write-only ? 0x28 key word 3 register aes_keyw3r write-only ? 0x2c key word 4 register aes_keyw4r write-only ? 0x30-0x3c reserved ??? 0x40 input data 1 regist er aes_idata1r write-only ? 0x44 input data 2 regist er aes_idata2r write-only ? 0x48 input data 3 regist er aes_idata3r write-only ? 0x4c input data 4 regist er aes_idata4r write-only ? 0x50 output data 1 register aes_odata1r read-only 0x0 0x54 output data 2 register aes_odata2r read-only 0xc01f0000 0x58 output data 3 register aes_odata3r read-only 0x0 0x5c output data 4 register aes_odata4r read-only 0x0 0x60 initialization vector 1 register aes_iv1r write-only ? 0x64 initialization vector 2 register aes_iv2r write-only ? 0x68 initialization vector 3 register aes_iv3r write-only ? 0x6c initialization vector 4 register aes_iv4r write-only ? 0x70 - 0xfc reserved ??? 0x100-0x124 reserved for the pdc ???
499 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.1 aes control register register name: aes_cr access type: write-only start: start processing 0 = no effect 1 = starts manual encryption/decryption process. swrst: software reset 0 = no effect. 1 = resets the aes. a software triggered hardware re set of the aes inte rface is performed. loadseed: random number generator seed loading 0 = no effect. 1 = loads a new seed in the embedded random number generator used for the different countermeasures. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????load seed 15 14 13 12 11 10 9 8 ???????swrst 76543210 ???????start
500 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.2 aes mode register name: aes_mr access type: read/write cipher: processing mode 0 = decrypts data. 1 = encrypts data. procdly: processing delay the processing time repr esents the number of clock cycle s that the aes needs in order to perform one en cryption/decryp- tion with no countermeasures activated. note: the best performance is achieved with procdly equal to 0. smod: start mode opmod: operation mode 31 30 29 28 27 26 25 24 ??? ctype 23 22 21 20 19 18 17 16 ckey ? cfbs 15 14 13 12 11 10 9 8 lod opmod ? ? smod 76543210 procdly ? ? ? cipher smod description 00manual mode 01auto mode 10 pdc mode lod = 0: the encrypted/decrypted data are available at the address specified in the receive pointer registers (aes_rpr, aes_rnpr). lod = 1: the encrypted/decrypted data are available in the output data registers. 11reserved opmod description 0 0 0 ecb: electronic code book mode 0 0 1 cbc: cipher block chaining mode 0 1 0 ofb: output feedback mode 0 1 1 cfb: cipher feedback mode 1 0 0 ctr: counter mode others reserved processing time 12 procdly 1 + () =
501 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary lod: last output data mode 0 = no effect. after each end of encryption/decryption, the output data is av ailable either on the output data registers (manual and auto modes), or at the address specified in the receive buffer pointer (pdc mode). in manual and auto modes, the datrdy flag is cleared when at least one of the output data registers is read. 1 = the datrdy flag is cleared when at leas t one of the input data registers is written. no more output data register reads is necessary between consecutive encry ptions/decryptions (see ?last output data mode? on page 494 ). warning : in pdc mode, reading to the output data registers before the last data encryption/decryption process may lead to unpredictable results. cfbs: cipher feedback data size ckey: countermeasure key this field should be written with the value 0xe to allow ctype field changes. if the field is written with a different value, changes ma de through the ctype field will not be taken into account. note: ckey field is write-only. ctype: countermeasure type note: all the countermeasures are enabled by default. note: ctype field is write-on ly and can only be modified if ckey is correctly set. cfbs description 0 0 0 128-bit 0 0 1 64-bit 0 1 0 32-bit 0 1 1 16-bit 1008-bit others reserved ctype description x x x x 0 countermeasure type 1 is disabled x x x x 1 countermeasure type 1 is enabled x x x 0 x countermeasure type 2 is disabled x x x 1 x countermeasure type 2 is enabled x x 0 x x countermeasure type 3 is disabled x x 1 x x countermeasure type 3 is enabled x 0 x x x countermeasure type 4 is disabled x 1 x x x countermeasure type 4 is enabled 0 x x x x countermeasure type 5 is disabled 1 x x x x countermeasure type 5 is enabled
502 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.3 aes interrupt enable register name: aes_ier access type: write-only datrdy: data ready interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable urad: unspecified register access detection interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
503 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.4 aes interrupt disable register name: aes_idr access type: write-only datrdy: data ready interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable urad: unspecified register acce ss detection interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
504 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.5 aes interrupt mask register name: aes_imr access type: read-only datrdy: data ready interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask urad: unspecified register access detection interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
505 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.6 aes interrupt status register name: aes_isr access type: read-only datrdy: data ready 0 = output data is not valid. 1 = encryption or decryption process is completed. datrdy is cleared when a manual encryption/decryption occu rs (start bit in aes_cr) or when a software triggered hardware reset of the aes interface is performed (swrst bit in aes_cr). lod = 0 (aes_mr): in manual and auto mode, the datrdy flag can also be cleared when at least one of the output data registers is read. in pdc mode, datrdy is set and cleared automatically. lod = 1 (aes_mr): in manual and auto mode, the datrdy flag can also be cleared when at least one of the input data registers is written. in pdc mode, datrdy is set and cleared automatically. endrx: end of rx buffer 0 = the receive counter register has not reach ed 0 since the last writ e in aes_rcr or aes_rncr. 1 = the receive counter register has reached 0 since the last write in aes_rcr or aes_rncr. note: this flag must be used only in pdc mode with lod bit cleared. endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in aes_tcr or aes_tncr. 1 = the transmit counter regist er has reached 0 si nce the last write in aes_tcr or aes_tncr. note: this flag must be used only in pdc mode with lod bit set. rxbuff: rx buffer full 0 = aes_rcr or aes_rncr has a value other than 0. note: 1 = this flag must be used only in pdc mode with lod bit cleared. both aes_rcr and aes_rncr have a value of 0. txbufe: tx buffer empty 0 = aes_tcr or aes_tncr has a value other than 0. 1 = both aes_tcr and aes_t ncr have a value of 0. note: this flag must be used only in pdc mode with lod bit set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 urat ? ? ? urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
506 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary urad: unspecified register access detection status 0 = no unspecified register access has been detected since the last swrst. 1 = at least one unspecified register access has been detected since the last swrst. urad bit is reset only by the swrst bit in the aes_cr control register. urat: unspecified re gister access type: only the last unspecified re gister access type is available through the urat field. urat field is reset only by the swrst bit in the aes_cr control register. urat description 0 0 0 input data register written during the data processing in pdc mode. 0 0 1 output data register read during the data processing. 0 1 0 mode register written during the data processing. 0 1 1 output data register read during the sub-keys generation. 1 0 0 mode register written during the sub-keys generation. 1 0 1 write-only register read access. others reserved
507 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.7 aes key word x register name: aes_keywxr access type: write-only keywx: key word x the four 32-bit key word registers set the 128-bit cryptographic key used for encryption/decryption. keyw1 corresponds to the first word of the key and keyw4 to the last one. these registers are write-only to prevent the key from being read by another application. 37.4.8 aes input data x register name: aes_idataxr access type: write-only idatax: input data word x the four 32-bit input data registers set the 128-bit data block used for encryption/decryption. idata1 corresponds to the first word of the data to be encrypted/decrypted, and idata4 to the last one. these registers are write-only to prevent the input data from being read by another application. 31 30 29 28 27 26 25 24 keywx 23 22 21 20 19 18 17 16 keywx 15 14 13 12 11 10 9 8 keywx 76543210 keywx 31 30 29 28 27 26 25 24 idatax 23 22 21 20 19 18 17 16 idatax 15 14 13 12 11 10 9 8 idatax 76543210 idatax
508 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 37.4.9 aes output data x register name: aes_odataxr access type: read-only odatax: output data x the four 32-bit output data registers contain the 128-bit data block that has been encrypted/decrypted. odata1 corresponds to the first word, odata4 to the last one. 37.4.10 aes initialization vector x register name: aes_ivxr access type: write-only ivx: initialization vector x the four 32-bit initialization vector registers set the 128-bit in itialization vector data block that is used by some modes of operation as an addit ional initial input. iv1 corresponds to the first word of the initialization vector, iv4 to the last one. these registers are write-only to prevent the initialization vector from being read by another application. for cbc, ofb and cfb modes, the initialization vector corresponds to the initialization vector. for ctr mode, it corresponds to the counter value. note: these registers are not used in ecb mode and must not be written. 31 30 29 28 27 26 25 24 odatax 23 22 21 20 19 18 17 16 odatax 15 14 13 12 11 10 9 8 odatax 76543210 odatax 31 30 29 28 27 26 25 24 ivx 23 22 21 20 19 18 17 16 ivx 15 14 13 12 11 10 9 8 ivx 76543210 ivx
509 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38. triple data encryption system (tdes) 38.1 description the triple data encryption standard (tdes) is compliant with the american fips (federal information processing standard) publication 46-3 specification. the tdes supports the four different confident iality modes of operation (ecb, cbc, ofb and cfb), specified in the fips (federal information proces sing standard) publication 81 and is compatible with the peripheral data controlle r channels for all of these modes, minimizing pro- cessor intervention for large buffer transfers. the 64-bit long keys and input data (and initialization vector for some modes) are each stored in two 32-bit registers (tdes_keyxwxr, tdes_idat axr and tdes_ivxr) wh ich are both write- only. as soon as the initialization vector, the input data and the key are configured, the encryp- tion/decryption process may be started. then the encrypted/decrypted data is ready to be read out on the two 32-bit output data registers (tdes_odataxr) or through the pdc channels. 38.2 product dependencies 38.2.1 power management the tdes may be clocked through the power management controller (pmc), so the program- mer must first configure the pmc to enable the tdes clock. 38.2.2 interrupt the tdes interface has an interrupt line connecte d to the advanced interrupt controller (aic). handling the tdes interrupt requires programming the aic before configuring the tdes.
510 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.3 functional description the data encryption standard (des) and the triple data encryption algorithm (tdea) specify fips-approved cryptographic algorithms that ca n be used to protect electronic data. the tdes bit in the tdes mode register (tdes_mr) is used to select either the single des or the triple des mode. encryption (enciphering) converts data to an unintelligible form called ciphertext. decrypting (deciphering) the ciphertext converts the data back into its original form, called plaintext. the cipher bit in the tdes mode register is used to choose between encryption and decryption. a des is capable of using cryptographic keys of 64 bits to encrypt and decr ypt data in blocks of 64 bits. this 64-bit key is defined in the key 1 word registers (tdes_key1wxr). a tdea key consists of three des keys, which is also referred to as a key bundle. these three 64-bit keys are defined, respectively, in the key 1, 2 and 3 word registers (tdes_key1wxr, tdes_key2wxr and tdes_k ey3wxr). in triple des mode (tdesmod set to 1), the key- mod bit in the tdes mode register is used to choose between a two- and a three-key algorithm: ? in three-key encryption mode, the data is first encrypted with key 1, then decrypted using key 2 and then encrypted with key 3. ? in three-key decryption mode, the data is decrypted with key 3, then encrypted with key 2 and then decrypted using key 1. ? in two-key encryption mode, the data is first encrypted with key 1, then decrypted using key 2 and then encrypted with key 1. ? in two-key decryption mode, the data is decrypted with key 1, then encrypted with key 2 and then decrypted using key 1. the input to the encryption processes of the cbc, cfb, and ofb modes includes, in addition to the plaintext, a 64-bit data block called the initialization vector (iv), which must be set in the ini- tialization vector registers (tdes_ivxr). the initiali zation vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. 38.3.1 operation modes the tdes supports the following modes of operation: ecb: electronic code book cbc: cipher block chaining ofb: output feedback cfb: cipher feedback ? cfb8 (cfb where the length of the data segment is 8 bits) ? cfb16 (cfb where the length of the data segment is 16 bits) ? cfb32 (cfb where the length of the data segment is 32 bits) ? cfb64 (cfb where the length of the data segment is 64 bits) the data pre-processing, post-processing and data chaining for each mode are automatically performed. refer to the fips publication 81 for more complete information. these modes are selected by setting the opmod field in the tdes mode register (tdes_mr). in cfb mode, four data sizes are possible (8, 16, 32 and 64 bits), configurable by means of the cfbs field in the mode register. ( see ?tdes mode register? on page 518. ).
511 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.3.2 start modes the smod field in the tdes mode register (tdes_mr) allows selection of encryption (or decryption) start mode. 38.3.2.1 manual mode the sequence is as follows: write the 64-bit key(s) in the different key word registers (tdes_keyxwxr), depending on whether one, two or three keys are required. write the initialization vector (or counter) in the initialization vector registers (tdes_ivxr). note: the initialization vector registers concern all modes except ecb. set the bit datrdy (data ready) in the tdes interrupt enable register (tdes_ier), depending on whether an interrupt is required or not at the end of processing. write the data to be encrypted/decrypted in the authorized input data registers (see table 38-1 ). note: in 32-, 16- and 8-bit cfb mode, writing to tdes_idata2r register is not allowed and may lead to errors in processing. set the start bit in the tdes control register tdes_cr to begin the encryption or the decryption process. when the processing completes, the bit datrdy in the tdes interrupt status register (tdes_isr) raises. if an interrupt has been enabled by setting the bit datrdy in tdes_ier, the interrupt line of the tdes is activated. when the software reads one of the output data registers (tdes_odataxr), the datrdy bit is automatically cleared. 38.3.2.2 auto mode the auto mode is similar to manual mode, except that, as soon as the correct number of input data registers is written, processing is automat ically started without any action in the control register. 38.3.2.3 pdc mode the peripheral data controller (pdc) can be used in association with the tdes to perform an encryption/decryption of a buffer without any action by the software during processing. table 38-1. authorized input data registers operation mode input data registers to write ecb all cbc all ofb all cfb 64-bit all cfb 32-bit tdes_idata1r cfb 16-bit tdes_idata1r cfb 8-bit tdes_idata1r
512 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary in this starting mode, the type of the data transfer (byte, half-word or word) depends on the oper- ation mode as per table 38-2 . the sequence is as follows: write the 64-bit key(s) in the different key word registers (tdes_keyxwxr), depending on whether one, two or three keys are required. write the initialization vector (or counter) in the initialization vector registers (tdes_ivxr). note: the initialization vector registers concern all modes except ecb. set the transmit pointer register (tdes_tpr) to the address where the data buffer to encrypt/decrypt is stored and the receive pointer register (tdes_rpr) where it must be encrypted/decrypted. note: transmit and receive buffers can be identical. set the transmit and the receive counter registers (tdes_tcr and tdes_rcr) to the same value. this value must be a multiple of the data transfer type size (see table 38-2 ). note: the same requirements are necessary for the next pointer(s) and counter(s) of the pdc (tdes_tnpr, tdes_rnpr, tdes_tncr, tdes_rncr). if not already done, set the bit endrx (or rx buff if the next point ers and counters are used) in the tdes interrupt enable register (tdes_ier), depending on whether an interrupt is required or not at the end of processing. enable the pdc in transmission and reception to start the processing (tdes_ptcr). when the processing completes, the bit endrx (or rxbuff) in the tdes interrupt status register (tdes_isr) raises. if an interrupt has been enabled by setting the corresponding bit in tdes_ier, the interrupt line of the tdes is activated. 38.3.3 last output data mode this mode is used to generate cryptographic checksums on data (mac) using a cbc or a cfb encryption algorithm (see fips publication 81 appendix f ). after each end of encryption/decryption, the output data is available either on the output data registers for manual and auto mode or at the address specified in the receive buffer pointer for pdc mode (see table on page 514 ). the last output data bit (lod) in the tdes m ode register (tdes_mr) retrieves only the last data of several encryption/decryption processes. therefore, there is no need to define a read buffer in pdc mode. this data is only available on the output data registers (tdes_odataxr). table 38-2. data transfer type for different operation modes operation mode data transfer type (pdc) ecb word cbc word ofb word cfb 64-bit word cfb 32-bit word cfb 16-bit half-word cfb 8-bit byte
513 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.3.3.1 manual and auto modes if lod = 0: the datrdy flag is cleared when at least one of the output data registers is read. see figure 38-1 . figure 38-1. manual and auto modes with lod = 0 if the user does not want to read the output data registers between each encryption/decryption, the datrdy flag will not be clea red. if the datrdy flag is no t cleared, the us er will not be informed of the end of the encryptions/decryptions that follow. if lod = 1: the datrdy flag is cleared when at least one input data register is written, before the start of a new transfer. see figure 38-2 . no further output data register reads are necessary between consecutive encryptions/decryptions. figure 38-2. manual and auto modes with lod = 1 38.3.3.2 pdc mode if lod = 0: the end of the encryption/decryption is notified by the endrx (or rxbuff) flag rise see figure 38-3 . encryption or decryption process read the tdes_odataxr write start bit in tdes_cr (manual mode) datrdy write tdes_idataxr register(s) (auto mode) or write tdes_idataxr register(s) write start bit in tdes_cr (manual mode) write tdes_idataxr register(s) (auto mode) or encryption or decryption process datrdy
514 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 38-3. pdc mode with lod = 0: if lod = : the user must first wait for the endtx (or txbufe) flag rise, then for datrdy to ensure that the encryption/decryption is completed. see figure 38-4 . in this case, no receive buffers are required. the output data is only available on the output data registers (tdes_odataxr). figure 38-4. pdc mode with lod = 1: table 38-3 summarizes the di fferent cases. note: 1. depending on the mode, there are ot her ways of clearing the datrdy flag. see ?tdes interrupt status register? on page 523. warning : in pdc mode, reading to the output data registers before the last data transfer may lead to unpredictable result. enable pdc channels (receive and transmit channels) multiple encryption or decryption process endrx (or rxbuff) enable pdc channels (only transmit channels) multiple encryption or decryption process datrdy endtx (or txbufe) table 38-3. last output mode behavior versus start modes manual and auto modes pdc mode lod = 0 lod = 1 lod = 0 lod = 1 datrdy flag clearing condition (1) at least one output data register must be read at least one input data register must be written not used managed by the pdc encrypted/decrypted data result location in the output data registers in the output data registers at the address specified in the receive pointer register (tdes_rpr) in the output data registers end of encryption/ decryption datrdy datrdy endrx (or rxbuff) endtx (or txbufe) then datrdy
515 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.3.4 security features when an unspecified register ac cess occurs, the urad bit in th e interrupt status register (tdes_isr) raises. its source is then reported in the unspecified register access type field (urat). only the last unspecified register access is available through the urat field. several kinds of unspecified register accesses can occur: input data register written during the data processing in pdc mode output data register read during the data processing mode register written during the data processing write-only register read access the urad bit and the urat field can only be rese t by the swrst bit in the tdes_cr control register.
516 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4 triple des (tde s) user interface table 38-4. tdes 128-bit register mapping offset register regist er name read/write reset 0x00 control register tdes_cr write-only ? 0x04 mode register tdes_mr read/write 0x2 0x08-0x0c reserved ??? 0x10 interrupt enable register tdes_ier write-only ? 0x14 interrupt disable register tdes_idr write-only ? 0x18 interrupt mask register tdes_imr read-only 0x0 0x1c interrupt status register tdes_isr read-only 0x0000001e 0x20 key 1 word 1 register tdes_key1w1r write-only ? 0x24 key 1 word 2 register tdes_key1w2r write-only ? 0x28 key 2 word 1 register tdes_key2w1r write-only ? 0x2c key 2 word 2 register tdes_key2w2r write-only ? 0x30 key 3 word 1 register tdes_key3w1r write-only ? 0x34 key 3 word 2 register tdes_key3w2r write-only ? 0x38-0x3c reserved ??? 0x40 input data 1 register tdes_idata1r write-only ? 0x44 input data 2 register tdes_idata2r write-only ? 0x48-0x4c reserved ??? 0x50 output data 1 register tdes_odata1r read-only 0x0 0x54 output data 2 register tdes_odata2r read-only 0x0 0x58-0x5c reserved ??? 0x60 initialization vector 1 register tdes_iv1r write-only ? 0x64 initialization vector 2 register tdes_iv2r write-only ? 0x68 - 0xfc reserved ??? 0x100-0x124 reserved for the pdc ???
517 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.1 tdes control register register name: tdes_cr access type: write-only start: start processing 0 = no effect 1 = starts manual encryption/decryption process. swrst: software reset 0 = no effect. 1 = resets the tdes. a software triggered hardware reset of the tdes interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????swrst 76543210 ???????start
518 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.2 tdes mode register name: tdes_mr access type: read/write cipher: processing mode 0 = decrypts data. 1 = encrypts data. tdesmod: single or triple des mode 0 = single des processing using tdes_key1wxr registers. 1= triple des proces sing using tdes_key1wxr, tdes_key2wx r and tdes_key3wxr registers. keymod: key mode 0 = three-key algorithm is selected. 1 = two-key algorithm is selected. there is no need to write tdes_key3wxr registers. smod: start mode opmod: operation mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????? cfbs 15 14 13 12 11 10 9 8 lod ? opmod ? ? smod 76543210 ? ? ? keymod ? ? tdesmod cipher smod description 00manual mode. 01auto mode. 10 pdc mode. lod = 0: the encrypted/decrypted data are available at the address specified in the receive pointer registers (tdes_rpr, tdes_rnpr). lod = 1: the encrypted/decrypted data are available in the output data registers. 11reserved opmod description 0 0 ecb: electronic code book mode 0 1 cbc: cipher block chaining mode 1 0 ofb: output feedback mode 1 1 cfb: cipher feedback mode
519 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary lod: last output data mode 0 = no effect. after each end of encryption/decryption, the output data is av ailable either on the output data registers (manual and auto modes), or at the address specified in the receive buffer pointer (pdc mode). in manual and auto modes, the datrdy flag is cleared when at least one of the output data registers is read. 1 = the datrdy flag is cleared when at leas t one of the input data registers is written. no more output data register reads are necessary between consecutive encryptions/decryptions ( see ?last output data mode? on page 512. ). warning : in pdc mode, reading to the output data registers before the last data encryption/decryption process may lead to unpredictable result. cfbs: cipher feedback data size cfbs description 0 0 64-bit 0 1 32-bit 1 0 16-bit 1 1 8-bit
520 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.3 tdes interrupt enable register name: tdes_ier access type: write-only datrdy: data ready interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable urad: unspecified register access detection interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
521 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.4 tdes interrupt disable register name: tdes_idr access type: write-only datrdy: data ready interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable urad: unspecified register acce ss detection interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
522 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.5 tdes interrupt mask register name: tdes_imr access type: read-only datrdy: data ready interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask urad: unspecified register access detection interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
523 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.6 tdes interrupt status register name: tdes_isr access type: read-only datrdy: data ready 0 = output data is not valid. 1 = encryption or decryption process is completed. datrdy is cleared when a manual encryption/decryption occurs (start bit in tdes_cr) or when a software triggered hardware reset of the tdes interface is performed (swrst bit in tdes_cr). lod = 0 (tdes_mr): in manual and auto mode, the datrdy flag can also be cleared when at least one of the output data registers is read. in pdc mode, datrdy is set and cleared automatically. lod = 1 (tdes_mr): in manual and auto mode, the datrdy flag can also be cleared when at least one of the input data registers is written. in pdc mode, datrdy is set and cleared automatically. endrx: end of rx buffer 0 = the receive counter re gister has not reached 0 since the last write in tdes_rcr or tdes_rncr. 1 = the receive counter register has reached 0 since the last write in tdes_rcr or tdes_rncr. note: this flag must be used only in pdc mode with lod bit cleared. endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in tdes_tcr or tdes_tncr. 1 = the transmit counter register has reached 0 since the last write in tdes_tcr or tdes_tncr. note: this flag must be used only in pdc mode with lod bit set. rxbuff: rx buffer full 0 = tdes_rcr or tdes_rncr has a value other than 0. note: 1 = this flag must be used only in pdc mode with lod bit cleared. both tdes_rcr and tdes_rncr have a value of 0. txbufe: tx buffer empty 0 = tdes_tcr or tdes_tncr has a value other than 0. 1 = both tdes_tcr and tdes_tncr have a value of 0. note: this flag must be used only in pdc mode with lod bit set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 urat ? ? ? urad 76543210 ? ? ? txbufe rxbuff endtx endrx datrdy
524 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary urad: unspecified register access detection status 0 = no unspecified register access has been detected since the last swrst. 1 = at least one unspecified register access has been detected since the last swrst. urad bit is reset only by the swrst bit in the tdes_cr control register. urat: unspecified re gister access type: only the last unspecified re gister access type is available through the urat field. urat field is reset only by the swrst bit in the tdes_cr control register. urat description 0 0 input data register written during the data processing in pdc mode. 0 1 output data register read during the data processing. 1 0 mode register written during the data processing. 1 1 write-only register read access.
525 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.7 tdes key 1 word x register name: tdes_key1wxr access type: write-only key1wx: key 1 word x the two 32-bit key 1 word registers allow to set the 64-bit cryptographic key used for encryption/decryption. key1w1 corresponds to the first word of the key and key1w2 to the last one. these registers are write-only to prevent the key from being read by another application. 38.4.8 tdes key 2 word x register name: tdes_key2wxr access type: write-only key2wx: key 2 word x the two 32-bit key 2 word registers allow to set the 64-bit cryptographic key used for encryption/decryption. key2w1 corresponds to the first word of the key and key2w2 to the last one. these registers are write-only to prevent the key from being read by another application. note: key2wxr registers are not used in des mode. 31 30 29 28 27 26 25 24 key1wx 23 22 21 20 19 18 17 16 key1wx 15 14 13 12 11 10 9 8 key1wx 76543210 key1wx 31 30 29 28 27 26 25 24 key2wx 23 22 21 20 19 18 17 16 key2wx 15 14 13 12 11 10 9 8 key2wx 76543210 key2wx
526 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.9 tdes key 3 word x register name: tdes_key3wxr access type: write-only key3wx: key 3 word x the two 32-bit key 3 word registers allow to set the 64-bit cryptographic key used for encryption/decryption. key3w1 corresponds to the first word of the key and key3w2 to the last one. these registers are write-only to prevent the key from being read by another application. note: key3wxr registers are not us ed in des mode a nd tdes with two-key algorithm selected. 38.4.10 tdes input data x register name: tdes_idataxr access type: write-only idatax: input data x the two 32-bit input data registers allow to set the 64-bit data block used for encryption/decryption. idata1 corresponds to the first word of the data to be encrypted/decrypted, and idata2 to the last one. these registers are write-only to prevent the input data from being read by another application. 31 30 29 28 27 26 25 24 key3wx 23 22 21 20 19 18 17 16 key3wx 15 14 13 12 11 10 9 8 key3wx 76543210 key3wx 31 30 29 28 27 26 25 24 idatax 23 22 21 20 19 18 17 16 idatax 15 14 13 12 11 10 9 8 idatax 76543210 idatax
527 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 38.4.11 tdes output data x register name: tdes_odataxr access type: read-only odatax: output data x the two 32-bit output data registers contain the 64-bit data block which has been encrypted/decrypted. odata1 corresponds to the first word, odata2 to the last one. 38.4.12 tdes initialization vector x register name: tdes_ivxr access type: write-only ivx: initialization vector x the two 32-bit initialization vector registers are used to set the 64-bit initialization vector data block, which is used by so me modes of operation as an additional initial input. iv1 corresponds to the first word of the initialization vector, iv2 to the last one. these registers are write-only to prevent the initialization vector from being read by another application. note: these registers are not used fo r ecb mode and must not be written. 31 30 29 28 27 26 25 24 odatax 23 22 21 20 19 18 17 16 odatax 15 14 13 12 11 10 9 8 odatax 76543210 odatax 31 30 29 28 27 26 25 24 ivx 23 22 21 20 19 18 17 16 ivx 15 14 13 12 11 10 9 8 ivx 76543210 ivx
528 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary
529 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39. controller area network (can) 39.1 description the can controller provides all the features required to implement the serial communication protocol can defined by robert bosch gmbh, the can specification as referred to by iso/11898a (2.0 part a and 2.0 part b) for high speeds and iso/11519-2 for low speeds. the can controller is able to handle all types of frames (data, remote, error and overload) and achieves a bitrate of 1 mbit/sec. can controller accesses are made through configuration register s. 8 independent message objects (mailboxes) are implemented. any mailbox can be programmed as a reception buffer block (even non-consecutive buffers). for the reception of defined messages, one or several message objects can be masked with- out participating in the buffer feature. an interrupt is generated when the buffer is full. according to the mailbox configuration, the first message received can be locked in the can controller registers until the application acknowledg es it, or this message can be discarded by new received messages. any mailbox can be programmed for transmissi on. several transmission mailboxes can be enabled in the same time. a priority can be defined for each mailbox independently. an internal 16-bit timer is used to stamp eac h received and sent message. this timer starts counting as soon as the can controller is enabl ed. this counter can be reset by the applica- tion or automatically after a reception in the last mailbox in time triggered mode. the can controller offers optimized features to support the time triggered communication (ttc) protocol.
530 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.2 block diagram figure 39-1. can block diagram internal bus can interrupt canrx controller area network pio cantx error counter user interface pmc mck mailbox priority encoder mb0 mbx (x = number of mailboxes - 1) control & status can protocol controller mb1
531 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.3 application block diagram figure 39-2. application block diagram 39.4 i/o lines description 39.5 product dependencies 39.5.1 i/o lines the pins used for interfacing the can may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the desired can pins to their peripheral func- tion. if i/o lines of the can are not used by the application, they can be used for other purposes by the pio controller. 39.5.2 power management the programmer must first enable the can clock in the power management controller (pmc) before using the can. a low-power mode is defined for the can contro ller: if the application does not require can operations, the can clock can be stopped when not needed and be restarted later. before stopping the clock, the can controller must be in low-power mode to complete the current transfer. after restarting the clock, the application must disable the low-power mode of the can controller. 39.5.3 interrupt the can interrupt line is connected on one of the internal sources of the advanced interrupt controller. using the can interrupt requires the aic to be programmed first. note that it is not recommended to use the can interrupt line in edge-sensitive mode. software software can controller transceiver implementation layers can-based application layer can-based profiles can data link layer can physical layer table 39-1. i/o lines description name description type canrx can receive serial data input cantx can transmit serial data output
532 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.6 can controller features 39.6.1 can protocol overview the controller area network (can) is a multi-master serial communication protocol that effi- ciently supports real-time control with a very high level of security with bit rates up to 1 mbit/s. the can protocol supports four different frame types: data frames: they carry data from a transmitter node to the receiver nodes. the overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame. remote frames: a destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. the appropriate data source node then sends a data frame as a response to this node request. error frames: an error frame is generated by any node that detects a bus error. overload frames: they provide an extra delay between the preceding and the successive data frames or remote frames. the atmel can controller provides the cpu with full functionality of the can protocol v2.0 part a and v2.0 part b. it minimizes the cpu load in communication overhead. the data link layer and part of the physical layer are automatically handled by the can controller itself. the cpu reads or writes data or messages via the can controller mailboxes. an identifier is assigned to each mailbox. the can controller encapsulates or decodes data messages to build or to decode bus data frames. remote frames, error frames and overload frames are automatically handled by the can controller under supervision of the software application. 39.6.2 mailbox organization the can module has 8 buffers, also called channels or mailboxes. an identifier that corre- sponds to the can identifier is defined for ea ch active mailbox. message identifiers can match the standard frame identifier or the extended frame identifier. this identifier is defined for the first time during the can initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. severa l mailboxes can be configured with the same id. each mailbox can be configured in receive or in transmit mode independently. the mailbox object type is defined in the mot field of the can_mmrx register. 39.6.2.1 message acceptance procedure if the mide field in the can_midx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. once a new message is received, its id is masked with the can_mamx value and compared with the can_midx value. if accepted, the message id is copied to the can_midx register.
533 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-3. message acceptance procedure if a mailbox is dedicated to receiving several messages (a family of messages) with different ids, the acceptance mask defined in the can_ma mx register must mask the variable part of the id family. once a message is received, the application must decode the masked bits in the can_midx. to speed up the decoding, masked bits are grouped in the family id register (can_mfidx). for example, if the following message ids are handled by the same mailbox: id0 000011101000100100010010000100 0 11 00b id1 000011101000100100010010000100 0 11 01b id2 000011101000100100010010000100 0 11 10b id3 000011101000100100010010000100 0 11 11b id4 000011101000100100010010000100 1 11 00b id5 000011101000100100010010000100 1 11 01b id6 000011101000100100010010000100 1 11 10b id7 000011101000100100010010000100 1 11 11b the can_midx and can_mamx of mailbox x must be initialized to the corresponding values: can_midx = 000011101000100100010010000100 x 11 xxb can_mamx = 111111111111111111111111111111 0 11 00b if mailbox x receives a message with id6, then can_midx and can_mfidx are set: can_midx = 000011101000100100010010000100 1 11 10b can_mfidx = 00000000000000000000000000000000110b if the application associates a handler for each message id, it may define an array of pointers to functions: void (*phandler[8])(void); when a message is received, the correspondi ng handler can be invoked using can_mfidx register and there is no need to check masked bits: unsigned int mfid0_register; mfid0_register = get_can_mfid0_register(); // get_can_mfid0_register() returns the value of the can_mfid0 register phandler[mfid0_register](); can_midx can_mamx message received & & == message accepted message refused no yes can_mfidx
534 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.6.2.2 receive mailbox when the can module receives a message, it look s for the first available mailbox with the low- est number and compares the received message id with the mailbox id. if such a mailbox is found, then the message is stored in its data registers. depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application (receive only), or, if new messages with the same id are received, then they overwrite the previous ones (receive with overwrite). it is also possible to configure a mailbox in consumer mode. in this mode, after each transfer request, a remote frame is automatically sent. the first answer received is stored in the corre- sponding mailbox data registers. several mailboxes can be chained to receive a buffer. they must be configured with the same id in receive mode, except for the last one, which can be configured in receive with over- write mode. the last mailbox can be used to detect a buffer overflow. 39.6.2.3 transmit mailbox when transmitting a message, the message length and data are written to the transmit mail- box with the correct identifier. for each transmit mailbox, a priority is assigned. the controller automatically sends the message with the highest priority first (set with the field prior in can_mmrx register). it is also possible to configure a mailbox in producer mode. in this mode, when a remote frame is received, the mailbox data are sent automatically. by enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer. mailbox object type description receive the first message received is st ored in mailbox data registers. data remain available until the next transfer request. receive with overwrite the last message received is stored in mailbox data regist er. the next message always overwrites the previous one. the application has to check whether a new message has not overwritten the current one while reading the data registers. consumer a remote frame is sent by the mailbox. the answer received is stored in mailbox data register. this extends receive mailbox features. data remain available until the next transfer request. mailbox object type description tr a n s m i t the message stored in the mailbox data registers will try to win the bus arbitration immediately or later according to or not the time management unit configuration (see section 39.6.3 ). the application is notified that the message has been sent or aborted. producer the message prepared in the mailbox data registers will be sent after receiving the next remote frame. this extends transmit mailbox features.
535 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.6.3 time management unit the can controller integrates a free-running 16-bit internal timer. the counter is driven by the bit clock of the can bus line. it is enabled wh en the can controller is enabled (canen set in the can_mr register). it is automatically cleared in the following cases: after a reset when the can controller is in low-power mode is enabled (lpm bit set in the can_mr and sleep bit set in the can_sr) after a reset of the can controller (canen bit in the can_mr register) in time-triggered mode, when a message is accepted by the last mailbox (rising edge of the mrdy signal in the can_msr last_mailbox_number register). the application can also reset the internal timer by setting timrst in the can_tcr register. the current value of the internal timer is always accessible by reading the can_tim register. when the timer rolls-over from ffffh to 0000h, tovf (timer overflow) signal in the can_sr register is set. tovf bit in the can_sr regist er is cleared by reading the can_sr register. depending on the corresponding interrupt mask in the can_imr register, an interrupt is gen- erated while tovf is set. in a can network, some can devi ces may have a larger counter. in this case, the application can also decide to freeze the internal counter when the timer reaches ffffh and to wait for a restart condition from another device. this feature is enabled by setting timfrz in the can_mr register. the can_tim register is fr ozen to the ffffh value. a clear condition described above restarts the timer. a time r overflow (tovf) interrupt is triggered. to monitor the can bus activity, the can_tim register is copied to the can _timestp regis- ter after each start of frame or end of frame and a tstp interrupt is triggered. if teof bit in the can_mr register is set, the value is captured at each end of frame, else it is captured at each start of frame. depending on the corresponding mask in the can_imr register, an interrupt is generated while tstp is set in th e can_sr. tstp bit is cleared by reading the can_sr register. the time management unit can operate in one of the two following modes: timestamping mode: the value of the internal timer is captured at each start of frame or each end of frame time triggered mode: a mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. timestamping mode is enabled by clearing ttm field in the can_mr register. time triggered mode is enabled by setting ttm field in the can_mr register.
536 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.6.4 can 2.0 standard features 39.6.4.1 can bit timing configuration all controllers on a can bus must have the same bit rate and bit length. at different clock fre- quencies of the individual controllers, the bit rate has to be adjusted by the time segments. the can protocol specification partitions the nominal bit time into four different segments: figure 39-4. partition of the can bit time time quantum: the time quantum is a fixed unit of time der ived from the mck period. the total number of time quanta in a bit time is programmable from 8 to 25. sync seg: this part of the bit time is used to synchronize the various nodes on the bus. an edge is expected to lie within this segment. prop seg: this part of the bit time is used to compensate for the physical delay times within the network. it is twice the sum of the signal?s propagation time on the bus line, the input comparator delay, and the output driver delay. this parameter is defined in the propag field of the can_br register. phase seg1, phase seg2: the phase-buffer-segments are used to compensate for edge phase errors. these segments can be lengthened or shortened by resynchronization. these parameters are defined in the phase1 and phase2 fi elds of the can_br register. sample point: the sample point is the point in time at which the bus level is read and interpreted as the value of that resp ective bit. its lo cation is at the end of phase_seg1. if the smp field in the can_br register is set, then the incoming bit stream is sampled three times with a period of half a can clock period, centered on sample point. in the can controller, the length of a bit on the can bus is determined by the parameters (brp, propag, phase1 and phase2). the time quantum is calculated as follows: sync_seg prop_seg phase_seg1 phase_seg2 nominal bit time sample point t bit t csc t prs t phs1 t phs2 ++ + = t csc brp 1 + () mck ? =
537 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary to compensate for phase sh ifts between cloc k oscillators of different controllers on the bus, the can controller must resynchronize on any revelant signal edge of the current transmis- sion. the resynchronization shortenes or lengthenes the bit time such that the position of the sample point is shifted with regard to the detected edge. the resynchronization jump width (sjw) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization. figure 39-5. can bit timing example of bit timing determination for can baudrate of 500 kbit/s: mck = 48mhz can baudrate= 500kbit/s => bit time= 2us delay of the bus driver: 50 ns delay of the receiver: 30ns delay of the bus line (20m): 110ns the total number of time quanta in a bit time must be comprised between 8 and 25. if we fix the bit time to 16 time quanta: tcsc = 1 time quanta = bit time / 16 = 125 ns => brp = (tcsc x mck) - 1 = 5 the propagation segment time is equal to twice the sum of the signal?s propagation time on the bus line, the receiver delay and the output driver delay: tprs = 2 * (50+30+110) ns = 380 ns = 3 tcsc => propag = tprs/tcsc - 1 = 2 the remaining time for the two phase segments is: tphs1 + tphs2 = bit time - tcsc - tprs = (16 - 1 - 3)tcsc tphs1 + tphs2 = 12 tcsc t prs t csc propag 1 + () = t phs1 t csc phase1 1 + () = t phs2 t csc phase2 1 + () = t sjw t csc sjw 1 + () = sync_ seg prop_seg phase_seg1 phase_seg2 nominal bit time sample point transmission point mck can clock t csc t prs t phs1 t phs2
538 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary because this number is even, we choose tphs2 = tphs1 (else we would choose tphs2 = tphs1 + tcsc) tphs1 = tphs2 = (12/2) tcsc = 6 tcsc => phase1 = phase2 = tphs1/tcsc - 1 = 5 the resynchronization jump width must be comprised between 1 tcsc and the minimum of 4 tcsc and tphs1. we choose its maximum value: tsjw = min(4 tcsc,tphs1) = 4 tcsc => sjw = tsjw/tcsc - 1 = 3 finally: can_br = 0x0053255
539 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary can bus synchronization two types of synchronization are distinguished: ?hard sy nchronization? at the start of a frame and ?resynchronization? inside a frame. after a hard synchronization, the bit time is restarted with the end of the sync_seg segment, regardless of the phase error. resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge. the effect of resynchronization is the same as that of hard synchronization when the magni- tude of the phase error of the edge causing the resyn chronization is less than or equal to the programmed value of the resynchronization jump width (t sjw ). when the magnitude of the phase error is larger than the resynchronization jump width and the phase error is positive, then phase_seg1 is lengthened by an amount equal to the resynchronizatio n jump width. the phase error is neg ative, then phase_seg2 is shorten ed by an amount equal to the resynchronizatio n jump width. figure 39-6. can resynchronization autobaud mode the autobaud feature is enabled by setting the abm field in the can_mr register. in this mode, the can controller is only listening to the line without acknowledging the received mes- sages. it can not send any message. the errors flags are updated. the bit timing can be adjusted until no error occurs (good configuration found). in this mode, the error counters are sync_ seg prop_seg phase_seg1 phase_seg2 sync_ seg prop_seg phase_seg1 phase_seg2 phase error phase error (max tsjw) sync_ seg sync_ seg sync_ seg prop_seg phase_seg1 phase_seg2 sync_ seg phase_seg2 sync_ seg prop_seg phase_seg1 phase_ seg2 sync_ seg phase_seg2 phase error nominal sample point sample point after resynchronization nominal sample point sample point after resynchronization the phase error is positive (the transmitter is slower than the receiver) received data bit received data bit nominal bit time (before resynchronization) bit time with resynchronization bit time with resynchronization phase error (max tsjw) nominal bit time (before resynchronization) the phase error is negative (the transmitter is faster than the receiver)
540 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary frozen. to go back to the standard mode, the abm bit must be cleared in the can_mr register. 39.6.4.2 error detection there are five different error types that are not mutually exclusive. each error concerns only specific fields of the can data frame (refer to the bosch can specification for their correspondence): crc error (cerr bit in the can_sr register): with the crc, the transmitter calculates a checksum for the crc bit sequence from the start of frame bit until the end of the data field. this crc sequence is tr ansmitted in the crc field of the data or remote frame. bit-stuffing error (serr bit in the can_sr register): if a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an error frame starting with the next bit-time. bit error (berr bit in can_sr register): a bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. an error frame is generated and starts with the next bit time. form error (ferr bit in the can_sr register): if a transmitter detects a dominant bit in one of the fix-formatted segments crc delimiter, ack delimiter or end of frame, a form error has occurred and an error frame is generated. acknowledgment error (aerr bit in the can_sr register): the transmitter checks the acknowledge slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. if this is the case, at least one other node has received the frame correctly. if not, an acknowledge error has occu rred and the transmitter will start in the next bit-time an error frame transmission. fault confinement to distinguish between temporary and permanent failures, every can controller has two error counters: rec (receive error counter) and tec (transmit error counter). the counters are incremented upon detected errors and respective ly are decremented upon correct transmis- sions or receptions. depending on the counter values, the state of the node changes: the initial state of the can controller is error active, meaning that the controller can send error active flags. the controller changes to the error passive state if there is an accumulation of errors. if the can controller fails or if there is an extreme accumulation of errors, there is a state transition to bus off.
541 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-7. line error mode an error active unit takes part in bus communication and sends an active error frame when the can controller detects an error. an error passive unit cannot send an active error frame. it takes part in bus communication, but when an error is detected, a passive error frame is sent. also, after a transmission, an error passive unit waits before initiating furthe r transmission. a bus off unit is not allowed to have any influence on the bus. for fault confinement, two errors counters (tec and rec) are implemented. these counters are accessible via the can_ecr register. the state of the can controller is automatically updated according to these counter values. if the can controller is in error active state, then the erra bit is set in the can_sr register. the corresponding interrupt is pending while the interrupt is not masked in the can_imr register. if the can controller is in error passive mode, then the errp bit is set in the can_sr register and an interrupt remains pending while the errp bit is set in the can_imr register. if the can is in bus-off mode, then the boff bit is set in the can_sr r egister. as for errp and erra, an interrupt is pending while the boff bit is set in the can_imr register. when one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the warn bit in can_sr register, but the node remains error active. the corresponding interrupt is p ending while the interrupt is set in the can_imr register. refer to the bosch can specification v2.0 for details on fault confinement. 39.6.4.3 overload the overload frame is provided to request a delay of the next data or remote frame by the receiver node (?request overload frame?) or to signal certain error conditions (?reactive over- load frame?) related to the intermission field respectively. reactive overload frames are transmitted after detection of the following error conditions: detection of a dominant bit during the first two bits of the intermission field detection of a dominant bit in the last bit of eof by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter the can controller can generate a request overload frame automatically after each message sent to one of the can controller mailboxes. th is feature is enabled by setting the ovl bit in the can_mr register. error active error passive bus off tec > 255 init tec > 127 or rec > 127 tec < 127 and rec < 127 128 occurences of 11 consecutive recessive bits or can controller reset
542 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary reactive overload frames are automatically handled by the can controller even if the ovl bit in the can_mr register is not set. an overload flag is generated in the same way as an error flag, but error counters do not increment. 39.6.5 low-power mode in low-power mode, the can controller cannot send or receive messages. all mailboxes are inactive. in low-power mode, the sleep signal in the ca n_sr register is set; otherwise, the wakeup signal in the can_sr register is set. these tw o fields are exclusive except after a can con- troller reset (wakeup and sleep are stuck at 0 after a reset). after power-up reset, the low- power mode is disabled and the wa keup bit is set in the can_sr register only after detec- tion of 11 consecutive recessive bits on the bus. 39.6.5.1 enabling low-power mode a software application can enab le low-power mode by setting the lpm bit in the can_mr global register. the can controller enters low-power mode once all pending transmit mes- sages are sent. when the can controller enters low-power mode, the sleep si gnal in the ca n_sr register is set. depending on the corresponding mask in the can_imr register, an interrupt is gener- ated while sleep is set. the sleep signal in the can_sr register is automatically clea red once wakeup is set. the wakeup signal is automatically cleared once sleep is set. reception is disabled while the sleep signal is set to one in the can_sr register . it is impor- tant to note that those messages with higher priority than the last message transmitted can be received between the lpm command and entry in low-power mode. once in low-power mode, the can controller clock can be switched off by programming the chip?s power management controller (pmc). the can controller drains only the static current. error counters are disabled while the sleep signal is set to one. thus, to enter low-power mode, the software application must: ? set lpm field in the can_mr register ? wait for sleep signal rising now the can controller clock can be disabled. this is done by programming the power man- agement controller (pmc).
543 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-8. enabling low-power mode 39.6.5.2 disabling low-power mode the can controller can be awake after detecting a can bus activity. bus activity detection is done by an external module that may be embedded in the chip. when it is notified of a can bus activity, the software a pplication disables low-power mode by programming the can controller. to disable low-power mode, the software application must: ? enable the can controller clock. this is done by programming the power management controller (pmc). ? clear the lpm field in the can_mr register the can controller synchronizes itself with the bus activity by checking for eleven consecutive ?recessive? bits. once synchronized, the wakeup signal in the can_sr register is set. depending on the corresponding mask in the can_imr register, an interrupt is generated while wakeup is set. the sleep signal in the can_sr register is automatically cleared once wakeup is set. wakeup signal is automatically cleare d once sleep is set. if no message is being sent on the bus, then the can controller is able to send a message eleven bit times after disabling low-power mode. if there is bus activity when low-power mode is disabled, the can controller is synchronized with the bus activity in the next interfra me. the previous message is lost (see figure 39-9 ). sleep (can_sr) mrdy (can_msr1) lpm (can_mr) lpen= 1 can bus mrdy (can_msr3) mailbox 1 mailbox 3 arbitration lost wakeup (can_sr) 0x0 can_tim
544 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-9. disabling low-power mode 39.7 functional description 39.7.1 can controller initialization after power-up reset, the can controller is di sabled. the can controll er clock must be acti- vated by the power management controller (pmc) and the can controller interrupt line must be enabled by the interrupt controller (aic). the can controller must be initialized with the can network parameters. the can_br regis- ter defines the sampling point in the bit time period. can_br must be set before the can controller is enabled by setting the canen field in the can_mr register. the can controller is enabled by setting the canen flag in the can_mr register. at this stage, the internal can controller state machine is reset, error counters are reset to 0, error flags are reset to 0. once the can controller is enabled, bus sync hronization is done automatically by scanning eleven recessive bits. the wakeup bit in the can_ sr register is automa tically set to 1 when the can controller is synchronized (wakeup and sleep are stuck at 0 after a reset). the can controller can start listening to the network in autobaud mode. in this case, the error counters are locked and a mailbox may be configured in receive mode. by scanning error flags, the can_br register values synchron ized with the network. once no error has been detected, the application disables the autobaud mode, clearing the abm field in the can_mr register. sleep (can_sr) mrdy (can_msrx) lpm (can_mr) can bus bus activity detected message x interframe synchronization wakeup (can_sr) message lost
545 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-10. possible initialization procedure 39.7.2 can controller interrupt handling there are two different types of interrupts. one type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. all interrupt sources can be masked by writing the corresponding field in the can_idr regis- ter. they can be unmasked by writing to the can_ier register. after a power-up reset, all interrupt sources are disabled (masked). the current mask status can be checked by reading the can_imr register. the can_sr register gives all interrupt source states. the following events may initiate one of the two interrupts: message object interrupt ? data registers in the mailbox object are available to the application. in receive mode, a new message was received. in transmit mode, a message was transmitted successfully. ? a sent transmission was aborted. system interrupts ? bus-off interrupt: the can module enters the bus-off state. ? error-passive interrupt: the can module enters error passive mode. ? error-active mode: the can module is ne ither in error passive mode nor in bus- off mode. errors ? no yes (abm == 1 and canen == 1) canen = 1 (abm == 0) abm = 0 and canen = 0 (can_sr or can_msrx) change can_br value end of initialization configure a mailbox in reception mode enable can controller interrupt line enable can controller clock (aic) (pmc)
546 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary ? warn limit interrupt: the can module is in error-active mode, but at least one of its error counter value exceeds 96. ? wake-up interrupt: this interrupt is generated after a wake-up and a bus synchronization. ? sleep interrupt: this interrupt is generated after a low-power mode enable once all pending messages in transmission have been sent. ? internal timer counter overflow interrupt: this interrupt is generated when the internal timer rolls over. ? timestamp interrupt: this interrupt is generated after the reception or the transmission of a start of frame or an end of frame. the value of the internal counter is copied in the can_timestp register. all interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. these interrupts are cleared by reading the can_sr register.
547 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.7.3 can controller message handling 39.7.3.1 receive handling two modes are available to configure a mailbox to receive messages. in receive mode , the first message received is stored in the mailbox data register. in receive with overwrite mode , the last message received is stored in the mailbox. simple receive mailbox a mailbox is in receive mode once the mot field in the can_mmrx register has been config- ured. message id and message acceptance mask must be set before the receive mode is enabled. after receive mode is enabled, the mrdy flag in the can_msr register is automatically cleared until the first message is received. when the first message has been accepted by the mailbox, the mrdy flag is set. an interrupt is pending for the mailbox while the mrdy flag is set. this interrupt can be masked depending on the mailbox flag in the can_imr global register. message data are stored in the mailbox data register until the software application notifies that data processing has ended. this is done by aski ng for a new transfer command, setting the mtcr flag in the can_mcrx register. this automatically clears the mrdy signal. the mmi flag in the can_msrx register notifies the software that a message has been lost by the mailbox. this flag is set when messages are received while mrdy is set in the can_msrx register. this flag is cleared by reading the can_msrs register. a receive mail- box prevents from overwriting the first message by new ones while mrdy flag is set in the can_msrx register. see figure 39-11 . figure 39-11. receive mailbox note: in the case of arm architecture, can_msrx, can_mdlx, can_mdhx can be read using an optimized ldm assembler instruction. receive with overwrite mailbox message 1 message 2 lost message 3 message 3 message 1 reading can_msrx reading can_mdhx & can_mdlx writing can_mcrx mmi (can_msrx) mrdy (can_msrx) can bus (can_mdlx can_mdhx) mtcr (can_mcrx) message id = can_midx
548 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary a mailbox is in receive with overwrite mode on ce the mot field in the can_mmrx register has been configured. message id and message acceptance masks must be set before receive mode is enabled. after receive mode is enabled, the mrdy flag in the can_msr register is automatically cleared until the first message is received. when the first message has been accepted by the mailbox, the mrdy flag is set. an interrupt is pending for the mailbox while the mrdy flag is set. this interrupt is masked depending on the mailbox flag in the can_imr global register. if a new message is received while the mrdy fl ag is set, this new message is stored in the mailbox data register, overwriting the previous message. the mmi flag in the can_msrx reg- ister notifies the software that a message has been dropped by the mailbox. this flag is cleared when reading the can_msrx register. the can controller may store a new message in the can data registers while the application reads them. to check that can_mdhx and can_ mdlx do not belong to different messages, the application must check the mmi field in the can_msrx register before and after reading can_mdhx and can_mdlx. if the mmi flag is set again after the data registers have been read, the software application has to re-read can_mdhx and can_mdlx (see figure 39-12 ). figure 39-12. receive with overwrite mailbox chaining mailboxes several mailboxes may be used to receive a buff er split into several messages with the same id. in this case, the mailbox with the lowest numb er is serviced first. in the receive and receive with overwrite modes, the field prior in the ca n_mmrx register has no effect. if mailbox 0 and mailbox 5 accept messages with the same id , the first message is received by mailbox 0 and the second message is received by mailbox 5. mailbox 0 must be configured in receive mode (i.e., the first message received is considered) and mailbox 5 must be configured in receive with overwrite mode. mailbox 0 cannot be configured in receive with overwrite mode; otherwise, all messages are accepted by this mailbox and mailbox 5 is never serviced. message 1 message 2 message 3 message 3 message 1 reading can_msrx reading can_mdhx & can_mdlx writing can_mcrx mmi (can_msrx) mrdy (can_msrx) can bus (can_mdlx can_mdhx) mtcr (can_mcrx) message id = can_midx message 4 message 2 message 4
549 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary if several mailboxes are chained to receive a bu ffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in receive mode. the first message received is handled by the first mailbox, the second one is refused by the first mail- box and accepted by the second mailbox, the last message is accepted by the last mailbox and refused by previous ones (see figure 39-13 ). figure 39-13. chaining three mailboxes to receive a buffer split into three messages if the number of mailboxes is not sufficient (the mmi flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see figure 39-14 ). mmi (can_msrx) mrdy (can_msrx) can bus message s1 reading can_msrx, can_msry and can_msrz writing mbx mby mbz in can_tcr reading can_mdh & can_mdl for mailboxes x, y and z mmi (can_msry) mrdy (can_msry) mmi (can_msrz) mrdy (can_msrz) message s2 message s3 buffer split in 3 messages
550 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-14. chaining three mailboxes to receive a buffer split into four messages 39.7.3.2 transmission handling a mailbox is in transmit mode once the mot field in the can_mmrx register has been con- figured. message id and message acceptance mask must be set before receive mode is enabled. after transmit mode is enabled, the mrdy flag in the can_msr register is automatically set until the first command is sent. when the mrdy flag is set, the software application can pre- pare a message to be sent by writing to the can_mdx registers. the message is sent once the software asks for a transfer command setting the mtcr bit and the message data length in the can_mcrx register. the mrdy flag remains at zero as long as the message has not been sent or aborted. it is important to note that no access to the mailbox data register is allowed while the mrdy flag is cleared. an interrupt is pending for the mailbox while the mrdy flag is set. this interrupt can be masked depending on the mailbox flag in the can_imr global register. it is also possible to send a remote frame sett ing the mrtr bit instead of setting the mdlc field. the answer to the remote frame is hand led by another reception mailbox. in this case, the device acts as a consumer but with the help of two mailboxes. it is possible to handle the remote frame emission and the answer reception using only one mailbox configured in con- sumer mode. refer to the section ?remote frame handling? on page 551 . several messages can try to win the bus arbitration in the same time. the message with the highest priority is sent first. several transfer request commands can be generated at the same time by setting mbx bits in the can_tcr register. the priority is set in the prior field of the can_mmrx register. priority 0 is the highest priority , priority 15 is the lowe st priority. thus it is possible to use a part of the message id to se t the prior field. if two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. thus if mailbox mmi (can_msrx) mrdy (can_msrx) can bus message s1 reading can_msrx, can_msry and can_msrz writing mbx mby mbz in can_tcr reading can_mdh & can_mdl for mailboxes x, y and z mmi (can_msry) mrdy (can_msry) mmi (can_msrz) mrdy (can_msrz) message s2 message s3 buffer split in 4 messages message s4
551 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first. setting the macr bit in the can_mcrx regist er aborts the transmission. transmission for several mailboxes can be aborted by writing mbx fields in the can_ma cr register. if the message is being sent when the abort command is set, then the application is notified by the mrdy bit set and not the mabt in the can_msrx register. otherwise, if the message has not been sent, then the mrdy and the mabt are set in the can_msr register. when the bus arbitration is lost by a mailbox message, the can controller tries to win the next bus arbitration with the same message if this on e still has the highest prio rity. messages to be sent are re-tried automatically until they win the bus arbitration. this feature can be disabled by setting the bit drpt in the can_mr register. in this case if the me ssage was not sent the first time it was transmitted to the can transceiver, it is automatically aborted. the mabt flag is set in the can_msrx register until the next transfer command. figure 39-15 shows three mbx message attempts being made (mrdy of mbx set to 0). the first mbx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the can transceiver. figure 39-15. transmitting messages 39.7.3.3 remote frame handling producer/consumer model is an efficient means of handling broadcasted messages. the push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. mtcr (can_mcrx) mrdy (can_msrx) can bus mbx message reading can_msrx writing can_mdhx & can_mdlx mbx message macr (can_mcrx) abort mbx message try to abort mbx message mabt (can_msrx)
552 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-16. producer / consumer model in pull mode, a consumer transmits a remote frame to the producer. when the producer receives a remote frame, it sends the answer accepted by one or many consumers. using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in transmit mode to send remote frames, and at least one in receive mode to capture the producer?s answer. the same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer. mailboxes can be configured in producer or consumer mode. a lonely mailbox can handle the remote frame and the answer. with 8 mailboxes, the can controller can handle 8 independent producers/consumers. producer configuration a mailbox is in producer mode once the mot fi eld in the can_mmrx register has been con- figured. message id and message acceptance masks must be set before receive mode is enabled. after producer mode is enabled, the mrdy flag in the can_msr register is automatically set until the first transfer command. the software application prepares data to be sent by writing to the can_mdhx and the can_mdlx registers, then by setting the mtcr bit in the can_mcrx register. data is sent after the recept ion of a remote frame as soon as it wins the bus arbitration. the mrdy flag remains at zero as long as the message has not been sent or aborted. no access to the mailbox data register can be done while mrdy flag is cleared. an interrupt is pending for the mailbox wh ile the mrdy flag is set. this in terrupt can be masked according to the mailbox flag in the can_imr global register. if a remote frame is received while no data are ready to be sent (signal mrdy set in the can_msrx register), then the mmi signal is set in the can_msrx register. this bit is cleared by reading the can_msrx register. the mrtr field in the can_msrx register has no meaning. this field is used only when using receive and receive with overwrite modes. can data frame can remote frame can data frame indication(s) request request(s) indications response confirmation(s) push model pull model producer producer consumer consumer
553 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary after a remote frame has been received, the mailbox functions like a transmit mailbox. the message with the highest priority is sent firs t. the transmitted message may be aborted by setting the macr bit in the can_mcr register. please refer to the section ?transmission handling? on page 550 . figure 39-17. producer handling consumer configuration a mailbox is in consumer mode once the mot field in the can_mmrx register has been con- figured. message id and message acceptance masks must be set before receive mode is enabled. after consumer mode is enabled, the mrdy flag in the can_msr register is automatically cleared until the first transfer request command. the software application sends a remote frame by setting the mtcr bit in the can_mcrx register or the mbx bit in the global can_tcr register. the application is notified of the answer by the mrdy flag set in the can_msrx register. the application can read the data contents in the can_mdhx and can_mdlx registers. an interrupt is pending for the mailbox while the mrdy flag is set. this interrupt can be masked according to the mailbox flag in the can_imr global register. the mrtr bit in the can_mcrx register has no effect. this field is used only when using transmit mode. after a remote frame has been sent, the consumer mailbox functions as a reception mailbox. the first message received is stored in the mailbox data registers. if other messages intended for this mailbox have been sent while the mrdy flag is set in the can_msrx register, they will be lost. the application is noti fied by reading the mmi field in the can_msrx register. the read operation automatically clears the mmi flag. if several messages are answered by the producer, the can controller may have one mailbox in consumer configuration, zero or several mailboxes in receive mode and one mailbox in receive with overwrite mode. in this case, the consumer mailbox must have a lower number than the receive with overwrite mailbox. the transfer command can be triggered for all mail- boxes at the same time by setting several mbx fields in the can_tcr register. mtcr (can_mcrx) mrdy (can_msrx) can bus remote frame message 1 message 1 message 2 (can_mdlx can_mdhx) mmi (can_msrx) remote frame remote frame message 2 reading can_msrx
554 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 39-18. consumer handling 39.7.4 can controller timing modes using the free running 16-bit internal timer, the can controller can be set in one of the two fol- lowing timing modes: timestamping mode: the value of the internal timer is captured at each start of frame or each end of frame. time triggered mode: the mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. timestamping mode is enabled by clearing the tt m bit in the can_mr register. time trig- gered mode is enabled by setting the ttm bit in the can_mr register. 39.7.4.1 timestamping mode each mailbox has its own timestamp value. each time a message is sent or received by a mailbox, the 16-bit value mtimestamp of the can_timestp register is transferred to the lsb bits of the can_msrx register. the value read in the can_msrx register corresponds to the internal timer value at the start of frame or the end of frame of the message handled by the mailbox. figure 39-19. mailbox timestamp mtcr (can_mcrx) mrdy (can_msrx) can bus remote frame message x message y message y (can_mdlx can_mdhx) mmi (can_msrx) remote frame message x teof (can_mr) mtimestamp (can_msrx) can_tim can bus mtimestamp (can_msry) message 1 message 2 start of frame timestamp (can_tstp) end of frame timestamp 1 timestamp 1 timestamp 2 timestamp 2
555 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.7.4.2 time triggered mode in time triggered mode, basic cycles can be split into several time windows. a basic cycle starts with a reference message. each time a window is defined from the reference message, a transmit operation should occu r within a pre-defined time window. a mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. figure 39-20. time triggered principle time trigger mode is enabled by setting the ttm field in the can_mr register. in time trig- gered mode, as in timestamp mode, the can_ timestp field captures the values of the internal counter, but the mtimestamp fields in the can_msrx registers are not active and are read at 0. synchronization by a reference message in time triggered mode, the internal timer counter is automatically reset when a new mes- sage is received in the last ma ilbox. this reset occurs after the reception of the end of frame on the rising edge of the mrdy signal in the ca n_msrx register. this allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window. transmitting within a time window a time mark is defined for each mailbox. it is defined in the 16-bit mtimemark field of the can_mmrx register. at each internal timer cl ock cycle, the value of the can_tim is com- pared with each mailbox time mark. when the internal timer counter reaches the mtimemark value, an internal timer event for the mailbox is generated for the mailbox. in time triggered mode, transmit operations ar e delayed until the internal timer event for the mailbox. the application prepares a message to be sent by setting the mtcr in the can_mcrx register. the message is not sent until the can_tim value is less than the mtimemark value defined in the can_mmrx register. if the transmit operation is failed, i.e., the message loses the bus arbitration and the next trans- mit attempt is delayed until the nex t internal time trigger event. this prevents overlapping the next time window, but the message is still pendin g and is retried in the next time window when can_tim value equals the mtimemark value. it is also possible to prevent a retry by setting the drpt field in the can_mr register. freezing the internal timer counter the internal counter can be frozen by setting timfrz in the can_mr register. this prevents an unexpected roll-over when the counter reaches ffffh. when this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. the tovf bit in the can_sr register is set when the counter reference message reference message global time time cycle time windows for messages
556 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary is frozen. the tovf bit in the can_sr regist er is cleared by reading the can_sr register. depending on the corresponding interrupt mask in the can_imr register, an interrupt is gen- erated when tovf is set. figure 39-21. time triggered operations mrdy (can_msrlast_mailbox_number) can_tim can bus mrdy (can_msrx) end of frame timer event x mtimemarkx == can_tim timer event y mrdy (can_msry) mtimemarky == can_tim cleared by software internal counter reset message x arbitration lost message y arbitration win reference message message y mrdy (can_msrlast_mailbox_number) can_tim can bus mrdy (can_msrx) end of frame timer event x mtimemarkx == can_tim cleared by software internal counter reset message x arbitration win reference message message x basic cycle time window basic cycle time window
557 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8 controller area networ k (can) user interface table 39-2. can memory map offset register name access reset state 0x0000 mode register can_mr read-write 0x0 0x0004 interrupt enable register can_ier write-only - 0x0008 interrupt disable register can_idr write-only - 0x000c interrupt mask register can_imr read-only 0x0 0x0010 status register can_sr read-only 0x0 0x0014 baudrate register can_br read/write 0x0 0x0018 timer register can_tim read-only 0x0 0x001c timestamp register can_timestp read-only 0x0 0x0020 error counter register can_ecr read-only 0x0 0x0024 transfer command register can_tcr write-only - 0x0028 abort command register can_acr write-only - 0x0100 - 0x01fc reserved ? ? ? 0x0200 mailbox 0 mode register can_mmr0 read/write 0x0 0x0204 mailbox 0 acceptance mask register can_mam0 read/write 0x0 0x0208 mailbox 0 id register can_mid0 read/write 0x0 0x020c mailbox 0 family id register can_mfid0 read-only 0x0 0x0210 mailbox 0 status register can_msr0 read-only 0x0 0x0214 mailbox 0 data low register can_mdl0 read/write 0x0 0x0218 mailbox 0 data high register can_mdh0 read/write 0x0 0x021c mailbox 0 control register can_mcr0 write-only - 0x0220 mailbox 1 mode register can_mmr1 read/write 0x0 0x0224 mailbox 1 acceptance mask register can_mam1 read/write 0x0 0x0228 mailbox 1 id register can_mid1 read/write 0x0 0x022c mailbox 1 family id register can_mfid1 read-only 0x0 0x0230 mailbox 1 status register can_msr1 read-only 0x0 0x0234 mailbox 1 data low register can_mdl1 read/write 0x0 0x0238 mailbox 1 data high register can_mdh1 read/write 0x0 0x023c mailbox 1 control register can_mcr1 write-only - ... ... ... ... -
558 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.1 can mode register name: can_mr access type: read/write canen: can controller enable 0 = the can controller is disabled. 1 = the can controller is enabled. lpm: disable/enable low power mode w power mode. 1 = enable low power m can controller enters low power mode once all pending messages have been transmitted. abm: disable/enable autobaud/listen mode 0 = disable autobaud/listen mode. 1 = enable autobaud/listen mode. ovl: disable/enable overload frame 0 = no overload frame is generated. 1 = an overload frame is generated after each successful rec eption for mailboxes configured in receive with/without over- write mode, producer and consumer. teof: timestamp messages at each end of frame 0 = the value of can_tim is captured in the can_timestp register at each start of frame. 1 = the value of can_tim is captured in the can_timestp register at each end of frame. ttm: disable/enable time triggered mode 0 = time triggered mode is disabled. 1 = time triggered mode is enabled. timfrz: enable timer freeze 0 = the internal timer continues to be incremented after it reached 0xffff. 1 = the internal timer stops incrementing after reaching 0xffff. it is restarted after a timer reset. see ?freezing the inter- nal timer counter? on page 555 . drpt: disable repeat 0 = when a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1 = when a transmit mailbox lose the bus arbitration, the transfe r request is automatically aborted. it automatically raises the mabt and mrdt flags in the corresponding can_msrx. 31 30 29 28 27 26 25 24 ????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 drpt timfrz ttm teof ovl abm lpm canen
559 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.2 can interrupt enable register name: can_ier access type: write-only mbx: mailbox x interrupt enable 0 = no effect. 1 = enable mailbox x interrupt. erra: error active mode interrupt enable 0 = no effect. 1 = enable erra interrupt. warn: warning limit interrupt enable 0 = no effect. 1 = enable warn interrupt. errp: error passive mode interrupt enable 0 = no effect. 1 = enable errp interrupt. boff: bus-off mode interrupt enable 0 = no effect. 1 = enable boff interrupt. sleep: sleep interrupt enable 0 = no effect. 1 = enable sleep interrupt. wakeup: wakeup interrupt enable 0 = no effect. 1 = enable sleep interrupt. tovf: timer overflow interrupt enable 0 = no effect. 1 = enable tovf interrupt. tstp: timestamp interrupt enable 0 = no effect. 1 = enable tstp interrupt. cerr: crc error interrupt enable 0 = no effect. 1 = enable crc error interrupt. 31 30 29 28 27 26 25 24 ? ? ? berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 ???????? 76543210 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0
560 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary serr: stuffing error interrupt enable 0 = no effect. 1 = enable stuffing error interrupt. aerr: acknowledgment error interrupt enable 0 = no effect. 1 = enable acknowledgment error interrupt. ferr: form error interrupt enable 0 = no effect. 1 = enable form error interrupt. berr: bit error interrupt enable 0 = no effect. 1 = enable bit error interrupt.
561 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.3 can interrupt disable register name: can_idr access type: write-only mbx: mailbox x interrupt disable 0 = no effect. 1 = disable mailbox x interrupt. erra: error active mode interrupt disable 0 = no effect. 1 = disable erra interrupt. warn: warning limit interrupt disable 0 = no effect. 1 = disable warn interrupt. errp: error passive mode interrupt disable 0 = no effect. 1 = disable errp interrupt. boff: bus-off mode interrupt disable 0 = no effect. 1 = disable boff interrupt. sleep: sleep interrupt disable 0 = no effect. 1 = disable sleep interrupt. wakeup: wakeup interrupt disable 0 = no effect. 1 = disable wakeup interrupt. tovf: timer overflow interrupt 0 = no effect. 1 = disable tovf interrupt. tstp: timestamp interrupt disable 0 = no effect. 1 = disable tstp interrupt. cerr: crc error interrupt disable 0 = no effect. 1 = disable crc error interrupt. 31 30 29 28 27 26 25 24 ? ? ? berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 ???????? 76543210 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0
562 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary serr: stuffing error interrupt disable 0 = no effect. 1 = disable stuffing error interrupt. aerr: acknowledgment error interrupt disable 0 = no effect. 1 = disable acknowledgment error interrupt. ferr: form error interrupt disable 0 = no effect. 1 = disable form error interrupt. berr: bit error interrupt disable 0 = no effect. 1 = disable bit error interrupt.
563 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.4 can interrupt mask register name: can_imr access type: read-only mbx: mailbox x interrupt mask 0 = mailbox x interrupt is disabled. 1 = mailbox x interrupt is enabled. erra: error active mode interrupt mask 0 = erra interrupt is disabled. 1 = erra interrupt is enabled. warn: warning limit interrupt mask 0 = warning limit interrupt is disabled. 1 = warning limit interrupt is enabled. errp: error passive mode interrupt mask 0 = errp interrupt is disabled. 1 = errp interrupt is enabled. boff: bus-off mode interrupt mask 0 = boff interrupt is disabled. 1 = boff interrupt is enabled. sleep: sleep interrupt mask 0 = sleep interrupt is disabled. 1 = sleep interrupt is enabled. wakeup: wakeup interrupt mask 0 = wakeup interrupt is disabled. 1 = wakeup interrupt is enabled. tovf: timer overflow interrupt mask 0 = tovf interrupt is disabled. 1 = tovf interrupt is enabled. tstp: timestamp interrupt mask 0 = tstp interrupt is disabled. 1 = tstp interrupt is enabled. cerr: crc error interrupt mask 0 = crc error interrupt is disabled. 1 = crc error interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? ? berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 ???????? 76543210 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0
564 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary serr: stuffing error interrupt mask 0 = bit stuffing error interrupt is disabled. 1 = bit stuffing error interrupt is enabled. aerr: acknowledgment error interrupt mask 0 = acknowledgment error interrupt is disabled. 1 = acknowledgment error interrupt is enabled. ferr: form error interrupt mask 0 = form error interrupt is disabled. 1 = form error interrupt is enabled. berr: bit error interrupt mask 0 = bit error interrupt is disabled. 1 = bit error interrupt is enabled.
565 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.5 can status register name: can_sr access type: read-only mbx: mailbox x event 0 = no event occurred on mailbox x. 1 = an event occurred on mailbox x. an event corresponds to mrdy, mabt fields in the can_msrx register. erra: error active mode 0 = can controller is not in error active mode 1 = can controller is in error active mode this flag is set depending on tec and rec counter values. it is set when node is neither in error passive mode nor in bus off mode. this flag is automatically reset wh en above condition is not satisfied. warn: warning limit 0 = can controller warning limit is not reached. 1 = can controller warning limit is reached. this flag is set depending on tec and rec counters values. it is set when at least one of the counters values exceeds 96. this flag is automatically reset wh en above condition is not satisfied. errp: error passive mode 0 = can controller is not in error passive mode 1 = can controller is in error passive mode this flag is set depending on tec and rec counters values. a node is error passive when tec counter is greater or equal to 128 (decimal) or when the rec counter is greater or equal to 128 (decimal) and less than 256. this flag is automatically reset wh en above condition is not satisfied. boff: bus off mode 0 = can controller is not in bus-off mode 1 = can controller is in bus-off mode this flag is set depending on tec counter value. a node is bu s off when tec counter is greater or equal to 256 (decimal). this flag is automatically reset wh en above condition is not satisfied. sleep: can controller in low power mode 0 = can controller is not in low power mode. 1 = can controller is in low power mode. 31 30 29 28 27 26 25 24 ovlsy tbsy rbsy berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 ???????? 76543210 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0
566 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary this flag is automatically reset when low power mode is disabled wakeup: can controller is not in low power mode 0 = can controller is in low power mode. 1 = can controller is not in low power mode. when a wakeup event occurs, the can cont roller is synchronized with the bus acti vity. messages can be transmitted or received. the can controller clock must be available when a w akeup event occurs. this flag is automatically reset when the can controller ente rs low power mode. tovf: timer overflow 0 = the timer has not rolled-over ffffh to 0000h. 1 = the timer rolls-over ffffh to 0000h. this flag is automatically clea red by reading can_sr register. tstp timestamp 0 = no bus activity has been detected. 1 = a start of frame or an end of frame has been detected (according to the teof field in the can_mr register). this flag is automatically cleare d by reading the can_sr register. cerr: mailbox crc error 0 = no crc error occurred duri ng a previous transfer. 1 = a crc error occurred during a previous transfer. a crc error has been detected during last reception. this flag is automatically clea red by reading can_sr register. serr: mailbox stuffing error 0 = no stuffing error occurred during a previous transfer. 1 = a stuffing error occurred during a previous transfer. a form error results from the detection of more than five consecutive bit with the same polarity. this flag is automatically clea red by reading can_sr register. aerr: acknowledgment error 0 = no acknowledgment error occurred during a previous transfer. 1 = an acknowledgment error occurred during a previous transfer. an acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. this flag is automatically cleared reading can_sr register. ferr: form error 0 = no form error occurred during a previous transfer 1 = a form error occurred during a previous transfer a form error results from violations on one or more of the fixed form of the following bit fields: ? crc delimiter ? ack delimiter ? end of frame ? error delimiter ? overload delimiter this flag is automatically clea red by reading can_sr register. berr: bit error 0 = no bit error occurred during a previous transfer. 1 = a bit error occurred during a previous transfer.
567 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary a bit error is set when the bit value monitored on the line is different from the bit value sent. this flag is automatically clea red by reading can_sr register. rbsy: receiver busy 0 = can receiver is not receiving a frame. 1 = can receiver is receiving a frame. receiver busy. this status bit is set by hardware while can receiver is acquiring or monitoring a frame (remote, data, over- load or error frame). it is automati cally reset when can is not receiving. tbsy: transmitter busy 0 = can transmitter is not transmitting a frame. 1 = can transmitter is transmitting a frame. transmitter busy. this status bit is set by hardware while can transmitter is generating a frame (remote, data, overload or error frame). it is automatically reset when can is not transmitting. ovlsy: overload busy 0 = can transmitter is not transmitting an overload frame. 1 = can transmitter is transmitting a overload frame. it is automatically reset when the bus is not transmitting an overload frame.
568 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.6 can baudrate register name: can_br access type: read/write any modification on one of the fields of the canbr register must be done while can module is disabled. phase2: phase 2 segment this phase is used to compensate the edge phase error. phase1: phase 1 segment this phase is used to compensate for edge phase error. propag: programming time segment this part of the bit time is used to compensa te for the physical delay times within the network. sjw: re-synchronization jump width to compensate for ph ase shifts between clock oscillators of different controllers on bus. the controller must re-synchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization. brp: baudrate prescaler. this field allows user to program the period of the ca n system clock to determine the individual bit timing. tcsc = (brp + 1) / mck smp: sampling mode 0 = the incoming bit stream is sampled once at sample point. 1 = the incoming bit stream is sampled three times with a period of a mck clock period, centered on sample point. smp sampling mode is automatically disabled if brp = 0. 31 30 29 28 27 26 25 24 ???????smp 23 22 21 20 19 18 17 16 ?brp 15 14 13 12 11 10 9 8 ? ? sjw ? propag 76543210 ? phase1 ? phase2 t phs2 t csc phase2 1 + () = t phs1 t csc phase1 1 + () = t prs t csc propag 1 + () = t sjw t csc sjw 1 + () =
569 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.7 can timer register name: can_tim access type: read-only timerx: timer this field represents the internal can controller 16-bit timer value. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 timer15 timer14 timer13 timer12 timer11 timer10 timer9 timer8 76543210 timer7 timer6 timer5 timer4 timer3 timer2 timer1 timer0
570 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.8 can timestamp register name: can_timestp access type: read-only mtimestampx: timestamp this field represents the internal can controller 16-bit timer value. if the teof bit is cleared in the can_mr register, the inte rnal timer counter value is captured in the mtimestamp field at each start of frame. else the value is captured at each end of frame. when the value is captured, the tstp flag is set in the can_sr register. if the tstp mask in the can_imr register is set, an interrupt is generate d while tstp flag is set in the can_sr register. this flag is cl eared by reading the can_sr register. note: the can_timestp register is reset when the can is di sabled then enabled thanks to the canen bit in the can_mr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mtimestamp 15 mtimestamp 14 mtimestamp 13 mtimestamp 12 mtimestamp 11 mtimestamp 10 mtimestamp 9 mtimestamp 8 76543210 mtimestamp 7 mtimestamp 6 mtimestamp 5 mtimestamp 4 mtimestamp 3 mtimestamp 2 mtimestamp 1 mtimestamp 0
571 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.9 can error counter register name: can_ecr access type: read-only rec: receive error counter when a receiver detects an error, rec will be increased by one, except when the detected error is a bit error while sending an active error flag or an overload flag. when a receiver detects a dominant bit as the first bit after sending an error flag, rec is increased by 8. when a receiver detects a bit error while sending an active erro r flag, rec is increased by 8. any node tolerates up to 7 co nsecutive dominant bits af ter sending an active error flag, passive error flag or overload flag. after detecting the 14th consecutive domina nt bit (in case of an active error flag or an over- load flag) or after detecting the 8th consecutive dominant bit following a passive error flag, and after each sequence of additional eight co nsecutive dominant bits, each receiver increases its rec by 8. after successful reception of a message, rec is decreased by 1 if it was between 1 and 127. if rec was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127. tec: transmit error counter when a transmitter sends an error flag , tec is increased by 8 except when ? the transmitter is error passive and detects an acknowledgment error because of not detecting a dominant ack and does not dete ct a dominant bit while sending its passive error flag. ? the transmitter sends an error flag because a stuff error occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant. when a transmitter detects a bit erro r while sending an active error flag or an overload flag, the tec will be increased by 8. any node tolerates up to 7 co nsecutive dominant bits af ter sending an active error flag, passive error flag or overload flag. after detecting the 14th consecutive domina nt bit (in case of an active error flag or an over- load flag) or after detecting the 8th consecutive dominant bit following a passive error flag, and after each sequence of additional eight co nsecutive dominant bits every tran smitter increases its tec by 8. after a successful transmission the tec is decreased by 1 unless it was already 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 tec 15 14 13 12 11 10 9 8 ???????? 76543210 rec
572 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.10 can transfer command register name: can_tcr access type: write-only this register initializes several transfer requests at the same time. mbx: transfer request for mailbox x this flag clears the mrdy and mabt flags in the corresponding can_msrx register. when several mailboxes are requested to be transmitted simult aneously, they are transmitted in turn, starting with the mail- box with the highest priority. if several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., mb0 will be tr ansferred before mb1). timrst: timer reset resets the internal timer counter. if the internal timer count er is frozen, this command automatically re-enables it. this command is useful in time triggered mode. 31 30 29 28 27 26 25 24 timrst??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 table 39-3. mailbox object type description receive it receives the next message. receive with overwrite this triggers a new reception. transmit sends data prepared in the mailbox as soon as possible. consumer sends a remote frame. producer sends data prepared in the mailbox after receiving a remote frame from a consumer.
573 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.11 can abort command register name: can_acr access type: write-only this register initializes several abort requests at the same time. mbx: abort request for mailbox x it is possible to set macr field (in the can_mcrx register) for each mailbox 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 table 39-4. mailbox object type description receive no action receive with overwrite no action tr a n s m i t cancels transfer request if the me ssage has not been transmitted to the can transceiver. consumer cancels the current transfer before the remote frame has been sent. producer cancels the current transfer. the next remote frame is not serviced.
574 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.12 can message mode register name: can_mmrx access type: read/write mtimemark: mailbox timemark this field is active in time triggered mode. transmit operatio ns are allowed when the internal timer counter reaches the mailbox timemark. see ?transmitting within a time window? on page 555 . in timestamp mode, mtimemark is set to 0. prior: mailbox priority this field has no effect in receive and receive with overwrite modes. in these modes, the mailbox with the lowest number is serviced first. when several mailboxes try to transmit a message at the same ti me, the mailbox with the highest pr iority is serviced first. if several mailboxes have the same priority, the mailbox with the lowest num ber is serviced first (i.e., mbx0 is serviced before mbx 15 if they have the same priority). mot: mailbox object type this field allows the user to define the type of the mailbox . all mailboxes are independently configurable. five different types are possible for each mailbox: 31 30 29 28 27 26 25 24 ????? mot 23 22 21 20 19 18 17 16 ???? prior 15 14 13 12 11 10 9 8 mtimemark 15 mtimemark 14 mtimemark 13 mtimemark 12 mtimemark 11 mtimemark 10 mtimemark9 mtimemark8 76543210 mtimemark7 mtimemark6 mtimemark5 mtimemark4 mtimemark3 mtimemark2 mtimemark1 mtimemark0 mot mailbox object type 000 mailbox is disabled. this prevents receiving or transmitting any messages with this mailbox. 001 reception mailbox. mailbox is configured for reception. if a message is received while the mailbox data register is full, it is discarded. 010 reception mailbox with overwrite. mailbox is configured for reception. if a message is received while the mailbox is full, it overwrites the previous message. 0 1 1 transmit mailbox. mailbox is configured for transmission. 100 consumer mailbox. mailbox is configured in reception but behaves as a transmit mailbox, i.e., it sends a remote frame and waits for an answer. 101 producer mailbox. mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a remote frame before sending its contents. 1 1 x reserved
575 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.13 can message acceptance mask register name: can_mamx access type: read/write to prevent concurrent access with the internal can core, the application must disable the mailbox before writing to can_mamx registers. midvb: complementary bits for identifier in extended frame mode acceptance mask for corresponding field of the message idvb register of the mailbox. midva: identifier for standard frame mode acceptance mask for corresponding field of the message idva register of the mailbox. mide: identifier version 0= compares idva from the received frame with th e can_midx register masked with can_mamx register. 1= compares idva and idvb from the received frame with the can_midx register masked with can_mamx register. 31 30 29 28 27 26 25 24 ? ? mide midva 23 22 21 20 19 18 17 16 midva midvb 15 14 13 12 11 10 9 8 midvb 76543210 midvb
576 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.14 can message id register name: can_midx access type: read/write to prevent concurrent access with the internal can core, the application must disable the mailbox before writing to can_midx registers. midvb: complementary bits for identifier in extended frame mode if mide is cleared, midvb value is 0. mide: identifier version this bit allows the user to define the version of messages pr ocessed by the mailbox. if set, mailbox is dealing with version 2.0 part b messages; otherwise, mailbox is dealing with version 2.0 part a messages. midva: identifier for standard frame mode 31 30 29 28 27 26 25 24 ? ? mide midva 23 22 21 20 19 18 17 16 midva midvb 15 14 13 12 11 10 9 8 midvb 76543210 midvb
577 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.15 can message family id register name: can_mfidx access type: read-only mfid: family id this field contains the concatenation of can_midx register bits masked by the can_mamx register. this field is useful to speed up message id decoding. the message acceptance procedure is described below. as an example: can_midx = 0x305a4321 can_mamx = 0x3ff0f0ff can_mfidx = 0x000000a3 31 30 29 28 27 26 25 24 ??? mfid 23 22 21 20 19 18 17 16 mfid 15 14 13 12 11 10 9 8 mfid 76543210 mfid
578 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.16 can message status register name: can_msrx access type: read only these register fields are updated each time a message transfer is received or aborted. mmi is cleared by reading the can_msrx register. mrdy, mabt are cleared by writing mtcr or macr in the can_mcrx register. warning: mrtr and mdlc state depends partly on the mailbox object type. mtimestamp: timer value this field is updated only when time-triggered operations are di sabled (ttm cleared in can_mr register). if the teof field in the can_mr register is cleared, timestamp is the internal timer value at the start of frame of the last message received or sent by the mailbox. if the teof field in the can_mr register is set, timestamp is the internal timer value at the end of frame of the last message received or sent by the mailbox. in time triggered mode, mtimestamp is set to 0. mdlc: mailbox data length code 31 30 29 28 27 26 25 24 ??????? mmi 23 22 21 20 19 18 17 16 mrdy mabt ? mrtr mdlc 15 14 13 12 11 10 9 8 mtimestamp 15 mtimestamp 14 mtimestamp 13 mtimestamp 12 mtimestamp 11 mtimestamp 10 mtimestamp 9 mtimestamp 8 76543210 mtimestamp 7 mtimestamp 6 mtimestamp 5 mtimestamp 4 mtimestamp 3 mtimestamp 2 mtimestamp 1 mtimestamp 0 mailbox object type description receive length of the first mailbox message received receive with overwrite length of the last mailbox message received transmit no action consumer length of the mailbox message received producer length of the mailbox message to be sent after the remote frame reception
579 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary mrtr: mailbox remote transmission request mabt: mailbox message abort an interrupt is triggered when mabt is set. 0 = previous transfer is not aborted. 1 = previous transfer has been aborted. this flag is cleared by writing to can_mcrx register mailbox object type description receive the first frame received has the rtr bit set. receive with overwrite the last frame received has the rtr bit set. transmit reserved consumer reserved. after setting the mot fi eld in the can_mmr, mrtr is reset to 1. producer reserved. after setting the mot field in the can_mmr, mrtr is reset to 0. mailbox object type description receive reserved receive with overwrite reserved transmit previous transfer has been aborted consumer the remote frame transfer request has been aborted. producer the response to the remote frame transfer has been aborted.
580 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary mrdy: mailbox ready an interrupt is triggered when mrdy is set. 0 = mailbox data registers can not be read/written by the software application. can_mdx are locked by the can_mdx. 1 = mailbox data registers can be read/written by the software application. this flag is cleared by writing to can_mcrx register. mmi: mailbox message ignored 0 = no message has been ignored during the previous transfer 1 = at least one message has been ignored during the previous transfer cleared by reading the can_msrx register. mailbox object type description receive at least one message has been received since the last mailbox transfer order. data from the first frame received can be read in the can_mdxx registers. after setting the mot field in the can_mmr, mrdy is reset to 0. receive with overwrite at least one frame has been received since the last mailbox transfer order. data from the last frame received can be read in the can_mdxx registers. after setting the mot field in the can_mmr, mrdy is reset to 0. transmit mailbox data have been transmitted. after setting the mot field in the can_mmr, mrdy is reset to 1. consumer at least one message has been received since the last ma ilbox transfer order. data from the first message received can be read in the can_mdxx registers. after setting the mot field in the can_mmr, mrdy is reset to 0. producer a remote frame has been received, mailbox data have been transmitted. after setting the mot field in the can_mmr, mrdy is reset to 1. mailbox object type description receive set when at least two messages intended for the mailbox have been sent. the first one is available in the mailbox data register. others have been ignored. a mailbox with a lower priority may have accepted the message. receive with overwrite set when at least two messages intended for the mailbox have been sent. the last one is available in the mailbox data register. previous ones have been lost. transmit reserved consumer a remote frame has been sent by the mailbox but several messages have been received. the first one is available in the mailbox data register. others have been ignored. another mailbox with a lower priority may have accepted the message. producer a remote frame has been received, but no data are available to be sent.
581 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.17 can message data low register name: can_mdlx access type: read/write mdl: message data low value when mrdy field is set in the can_msrx register, the lower 32 bits of a received message can be read or written by the software application. otherwise, the mdh value is locked by the can controller to send/receive a new message. in receive with overwrite, the can controller may modify mdl value while the software application reads mdh and mdl registers. to check that mdh and mdl do not belong to differ ent messages, the application has to check the mmi field in the can_msrx register. in this mode, the software application must re-read can_mdh and can_mdl, while the mmi bit in the can_msrx register is set. 31 30 29 28 27 26 25 24 mdl 23 22 21 20 19 18 17 16 mdl 15 14 13 12 11 10 9 8 mdl 76543210 mdl
582 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.18 can message data high register name: can_mdhx access type: read/write mdh: message data high value when mrdy field is set in the can_msrx re gister, the upper 32 bits of a received message are read or written by the soft- ware application. otherwise, the mdh value is locked by the can controller to send/receive a new message. in receive with overwrite, the can cont roller may modify mdh value while the so ftware application reads mdh and mdl registers. to check that mdh and mdl do not belong to differ ent messages, the application has to check the mmi field in the can_msrx register. in this mode, the software application must re-read can_mdh and can_mdl, while the mmi bit in the can_msrx register is set. 31 30 29 28 27 26 25 24 mdh 23 22 21 20 19 18 17 16 mdh 15 14 13 12 11 10 9 8 mdh 76543210 mdh
583 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 39.8.19 can message control register name: can_mcrx access type: write-only mdlc: mailbox data length code mrtr: mailbox remote transmission request consumer situations can be handled automatically by setting the mailbox object type in consumer. this requires only one mailbox. it can also be handled using two mailboxes, one in reception, the other in transmission. the mrtr and the mtcr bits must be set in the same time. 31 30 29 28 27 26 25 24 ?????? ?? 23 22 21 20 19 18 17 16 mtcr macr ? mrtr mdlc 15 14 13 12 11 10 9 8 ? ? ? ? ? ?? ? 76543210 ? ? ? ? ?? ?? mailbox object type description receive no action. receive with overwrite no action. transmit length of the mailbox message. consumer no action. producer length of the mailbox message to be sent after the remote frame reception. mailbox object type description receive no action receive with overwrite no action transmit set the rtr bit in the sent frame consumer no action, the rtr bit in the sent frame is set automatically producer no action
584 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary macr: abort request for mailbox x it is possible to set macr field for several mailboxes in the same time, setting several bits to the can_acr register. mtcr: mailbox transfer command this flag clears the mrdy and mabt flags in the can_msrx register. when several mailboxes are requested to be transmitted simult aneously, they are transmitted in turn. the mailbox with the highest priority is serviced first. if several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., mbx0 will be serv iced before mbx 15 if they have the same priority). it is possible to set mtcr for several mailboxes at the same time by writing to the can_tcr register. mailbox object type description receive no action receive with overwrite no action tr a n s m i t cancels transfer request if the me ssage has not been transmitted to the can transceiver. consumer cancels the current transfer before the remote frame has been sent. producer cancels the current transfer. the next remote frame will not be serviced. mailbox object type description receive allows the reception of the next message. receive with overwrite triggers a new reception. transmit sends data prepared in the mailbox as soon as possible. consumer sends a remote transmission frame. producer sends data prepared in the mailbox after receiving a remote frame from a consumer.
585 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40. ethernet mac 10/100 (emac) 40.1 overview the emac module implements a 10/100 ethernet mac compatible with the ieee 802.3 stan- dard using an address checker, statistics and co ntrol registers, receive and transmit blocks, and a dma interface. the address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis- ter for matching multicast and unicast addresses. it can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. the statistics register block contains register s for counting various types of event associated with transmit and receive operations. these register s, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with ieee 802.3. 40.2 block diagram figure 40-1. emac block diagram apb slave register interface dma interface address checker statistics registers control registers ethernet receive ethernet transmit mdio mii/rmii rx fifo tx fifo asb master
586 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.3 functional description figure 40-1 illustrates the different bl ocks of the emac module. the control registers drive the mdio interface, setup up dma activity, start frame transmission and select modes of operation such as full- or half-duplex. the receive block checks for valid preamble, fcs, alignment and length, and presents received frames to the address checking block and dma interface. the transmit block takes data from the dma interface, adds preamble and, if necessary, pad and fcs, and transmits data according to the csma/cd (carrier sense multiple access with col- lision detect) protocol. the start of transmission is deferred if crs (carrier sense) is active. if col (collision) becomes active during transmission, a jam se quence is asserted and the transmission is retried after a random back off. crs and col have no effect in full duplex mode. the dma block connects to external memory thr ough its asb bus interface. it contains receive and transmit fifos for buffering frame data. it loads the transmit fifo and empties the receive fifo using asb bus master operations. receive data is not sent to memory until the address checking logic has determined that the frame should be copied. receive or transmit frames are stored in one or more buffers. receive buffers have a fixed length of 128 bytes. transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. the dma block manages the transmit and receive framebuffer queues. these queues can hold mul- tiple frames. 40.3.1 memory interface frame data is transferred to and from the emac through the dma interface. all transfers are 32- bit words and may be single acce sses or bursts of 2, 3 or 4 word s. burst accesses do not cross sixteen-byte boundaries. bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. the dma controller performs six types of operation on the bus. in order of priority, these are: 1. receive buffer manager write 2. receive buffer manager read 3. transmit data dma read 4. receive data dma write 5. transmit buffer manager read 6. transmit buffer manager write 40.3.1.1 fifo the fifo depths are 28 bytes and 28 bytes and area function of the system clock speed, mem- ory latency and network speed. data is typically transferred into and out of the fifos in bursts of four words. for receive, a bus request is asserted when the fifo contains four words and has space for three more. for trans- mit, a bus request is generated when there is space for four words, or when there is space for two words if the next transfer is to be only one or two words. thus the bus latency must be less than the time it takes to load the fifo and transmit or receive three words (12 bytes) of data.
587 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary at 100 mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. in addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the fifos. for a 60 mhz master clock this takes 100 ns, making the bus latency requirement 860 ns. 40.3.1.2 receive buffers received frames, including crc/fc s optionally, are written to receive buffers stored in mem- ory. each receive buffer is 128 bytes long. the start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. the receive buffer start location is a word address. for the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. if the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes. each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. if the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zer oes except for the ?start of frame? bit and the offset bits, if appropriate. bit zero of the address field is written to one to show the buffer has been used. the receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. the final buff er descriptor status word contains the complete frame status. refer to table 40-1 for details of the receive buffer descriptor list. table 40-1. receive buffer descriptor entry bit function word 0 31:2 address of beginning of buffer 1 wrap - marks last descriptor in receive buffer descriptor list. 0 ownership - needs to be zero for the emac to write data to the receive buffer. the emac sets this to one once it has successfully written a frame to memory. software has to clear this bit before the buffer can be used again. word 1 31 global all ones broadcast address detected 30 multicast hash match 29 unicast hash match 28 external address match 27 reserved for future use 26 specific address register 1 match 25 specific address register 2 match 24 specific address register 3 match 23 specific address register 4 match 22 type id match 21 vlan tag detected (i.e., type id of 0x8100) 20 priority tag detected (i.e., type id of 0x8100 and null vlan identifier) 19:17 vlan priority (only valid if bit 21 is set)
588 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary to receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. bit zero must be written with zero. bit one is the wrap bit and indicates the last entry in the list. the start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. as soon as the receive block starts writing received frame data to the receive fifo, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. if the filter block then indicates that the frame should be copied to memory, the receive data dma operation starts writing data into the receive buffer. if an error occurs, the buffer is recov- ered. if the current buffer pointer has its wrap bit set or is the 1024 th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. otherwise, the next receive buffer location is read from the next word in memory. there is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. this is added with the valu e originally written to the receive buffer queue pointer register to produce a pointer into the list. a read of the receive buffer queue pointer reg- ister returns the pointer value, which is the queu e entry currently being accessed. the counter is reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. the value written to the receive buffer pointer regis- ter may be any word-aligned address, provided t hat there are at least 2048 word locations available between the pointer and the top of the memory. section 3.6 of the amba 2.0 specification states that bursts should not cross 1k boundaries. as receive buffer manager writes are bursts of two word s, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. as receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used . if a receive error is detected the receive buffer currently being written is recovered. previ- ous buffers are not recovered. software should search through the used bits in the buffer descriptors to find out how many frames have been received. it should be checking the start-of- frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes contin uously as more buffers are used. for crc errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored 16 concatenation format indicator (cfi) bit (only valid if bit 21 is set) 15 end of frame - when set the buffer contains the end of a frame. if end of frame is no t set, then the only other valid status are bits 12, 13 and 14. 14 start of frame - when set the buffer contains the start of a frame. if both bits 15 a nd 14 are set, then the buffer contains a whole frame. 13:12 receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. updated with the current values of the network configuration register. if jum bo frame mode is enabled through bit 3 of the network configuration register, then bits 13: 12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. 11:0 length of frame including fcs (if selected). bits 13:12 are also used if jumbo frame mode is selected. table 40-1. receive buffer descrip tor entry (continued) bit function
589 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary in a sequence of receive buffers. software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. for a properly working ethernet system, there s hould be no excessively long frames or frames greater than 128 bytes with crc/ fcs errors. collision fragments ar e less than 128 bytes long. therefore, it is a rare occurrence to find a frame fragment in a receive buffer. if bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. in this case, the dma block sets the buffer not available bit in the receive status register and triggers an interrupt. if bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. a receive overrun condition occurs when bus was not granted in time or because hresp was not ok (bus error). in a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. the next frame received with an address that is recognized reuses the buffer. if bit 17 of the network configuration register is set, the fcs of received frames shall not be cop- ied to memory. the frame length indicated in the receive status field shall be reduced by four bytes in this case. 40.3.1.3 transmit buffer frames to be transmitted are stored in one or more transmit buffers. transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in ieee standard 802.3. zero length buffers are allowed. the maximum number of buffers permitted for each transmit frame is 128. the start location for each transmit buffer is stored in memory in a list of transmit buffer descrip- tors at a location pointed to by the transmit buffer queue pointer register. each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. frames can be transmitted with or without automatic crc gen- eration. if crc is automatically generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. table 40-2 on page 590 defines an entry in the transmit buffer descriptor list. to transmit frames, the buffer descriptors must be initialized by writing an appro- priate byte address to bits 31 to 0 in the first word of each list entry. the second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted wit h crc and whether the bu ffer is the last bu ffer in the frame. after transmission, the control bits are written back to the second word of the first buffer along with the ?used? bit and other status information. bit 31 is the ?used? bit which must be zero when the control word is read if transmission is to happen. it is written to one when a frame has been transmitted. bits 27, 28 and 29 indicate various transmit error conditions. bit 30 is the ?wrap? bit which can be set for any buffer within a frame. if no wrap bit is encountered after 1024 descrip- tors, the queue pointer rolls over to the start in a similar fashion to the receive queue. the transmit buffer queue pointer register must not be written while transmit is active. if a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. if transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. note that disabling receive does not have the same effect on the receive queue pointer.
590 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary once the transmit queue is init ialized, transmit is activate d by writing to bit 9, the transmit start bit of the network control register. transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writ ing to the transmit halt bit of the network control register. (transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) rewrit ing the start bit while transmission is active is allowed. transmission control is implemented with a tx_go variable which is readable in the transmit sta- tus register at bit location 3. the tx_go variable is reset when: ? transmit is disabled ? a buffer descriptor with its ownership bit set is read ? a new value is written to the transmit buffer queue pointer register ? bit 10, tx_halt, of the network control register is written ? there is a transmit error such as too many retries or a transmit underrun. to set tx_go, write to bit 9, tx_start, of the network control register. transmit halt does not take effect until any ongoing transmit finishes. if a collision occurs during transmission of a multi- buffer frame, transmission automatically restarts from the first buffer of the frame. if a ?used? bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. transmission stops, tx_er is asserted and the fcs is bad. if transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. software needs to re-initialize the transmit queue after a trans- mit error. if transmission stops due to a ?used? bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written table 40-2. transmit buffer descriptor entry bit function word 0 31:0 byte address of buffer word 1 31 used. needs to be zero for the emac to read data from the tran smit buffer. the emac sets this to one for the first buffer of a frame once it has been successfully transmitted. software has to clear this bit before the buffer can be used again. note: this bit is only set for the first buffer in a frame unlike receive where all buffers have the used bit set once used. 30 wrap. marks last descriptor in transmit buffer descriptor list. 29 retry limit exceeded, transmit error detected 28 transmit underrun, occurs either when hresp is not ok (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame. 27 buffers exhausted in mid frame 26:17 reserved 16 no crc. when set, no crc is appended to the current frame. this bit only needs to be set for the last buffer of a frame. 15 last buffer. when set, this bit indicates the last buffer in the current frame has been reached. 14:11 reserved 10:0 length of buffer
591 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.3.2 transmit block this block transmits frames in accordance wi th the ethernet ieee 802.3 csma/cd protocol. frame assembly starts by adding preamble and the start frame delimiter. data is taken from the transmit fifo a word at a time. data is transmi tted least significant nibble first. if necessary, padding is added to increase the frame length to 60 bytes. crc is calculated as a 32-bit polyno- mial. this is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. if the no crc bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor crc are appended. in full-duplex mode, frames are transmitted immediately. back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. in half-duplex mode, the transmitter checks carrier s ense. if asserted, it waits for it to de-assert and then starts transmission afte r the interframe gap of 96 bit ti mes. if the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. the back-off time is based on an xor of the 10 least significant bits of the data coming from the transmit fifo and a 10-bit pseudo random number generator. the number of bits used depends on the number of collisions seen. after the first collision, 1 bit is used, after the second 2, and so on up to 10. above 10, all 10 bits are used. an error is indicated and no further attempts are made if 16 attempts cause collisions. if transmit dma underruns, bad crc is automati cally appended using the same mechanism as jam insertion and the tx_er signal is asserted. for a properly configured system, this should never happen. if the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a co llision. this provides a way of implementing flow control in half-duplex mode. 40.3.3 pause frame support the start of an 802.3 pause frame is as follows: the network configuration register contains a receive pause enable bit (13). if a valid pause frame is received, the pause time register is updated with the frame?s pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. an interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. if bit 13 is set in the network configuration register and the value of the pause time reg- ister is non-zero, no new frame is transmitted until the pause time register has decremented to zero. the loading of a new pause time, and hence the pausing of transmission, only occurs when the emac is configured for full-duplex operation. if the emac is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is st ill triggered. table 40-3. start of an 802.3 pause frame destination address source address type (mac control frame) pause opcode pause time 0x0180c2000001 6 bytes 0x8808 0x0001 2 bytes
592 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary a valid pause frame is defined as having a destin ation address that matches either the address stored in specific address register 1 or matches 0x0180c2000001 and has the mac control frame type id of 0x8808 and the pause opcode of 0x0001. pause frames that have fcs or other errors are treated as invalid and are discarded. valid pause frames received increment the pause frame received statistic register. the pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. for test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. if the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not. an interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the inte rrupt mask register). 40.3.4 receive block the receive block checks for valid preamble, fcs, alignment and length, presents received frames to the dma block and stores the frames destination address for use by the address checking block. if, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the dma bloc k. the dma block then ceases sending data to memory. at the end of frame reception, the receive block indicates to the dma block whether the frame is good or bad. the dma block recovers the current receive buffer if the frame was bad. the receive block signals the register block to increment the alignment error, the crc (fcs) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. the enable bit for jumbo frames in the network configuration register allows the emac to receive jumbo frames of up to 10240 bytes in size. this operation does not form part of the ieee802.3 specification and is disabled by default. when ju mbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 40.3.5 address checking block the address checking (or filter) block indicates to the dma block which receive frames should be copied to memory. whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame?s destination add ress. in this implementation of the emac, the frame?s source address is not checked. provided that bit 18 of the network configuration regis- ter is not set, a frame is not copied to memory if the emac is transmitting in half duplex mode at the time a destination address is received. if bit 18 of the network configuration register is set, frames can be received while transmitting in half-duplex mode. ethernet frames are transmitted a byte at a time, least significant bit first. the first six bytes (48 bits) of an ethernet frame make up the destination address. the first bit of the destination address, the lsb of the first byte of the frame, is the group/individual bit: this is one for multicast addresses and zero for unicast. the all ones address is the broadcast address, and a special case of multicast. the emac supports recognition of four specific addresses. each specific address requires two registers, specific address register bottom and specific address register top. specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. the addresses st ored can be specific, group, local or universal.
593 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the destination address of received frames is compared against the data stored in the specific address registers once they have been activated. the addresses are deactivated at reset or when their corresponding specific a ddress register bottom is written. they are activated when specific address register top is written. if a re ceive frame address matc hes an active address, the frame is copied to memory. the following example illustrates the use of the address match registers for a mac address of 21:43:65:87:a9:cb. preamble 55 sfd d5 da (octet0 - lsb) 21 da(octet 1) 43 da(octet 2) 65 da(octet 3) 87 da(octet 4) a9 da (octet5 - msb) cb sa (lsb) 00 sa 00 sa 00 sa 00 sa 00 sa (msb) 43 sa (lsb) 21 the sequence above shows the beginning of an et hernet frame. byte order of transmission is from top to bottom as shown. for a successful match to specific address 1, the following address matching registers must be set up: base address + 0x98 0x87654321 (bottom) base address + 0x9c 0x0000cba9 (top) and for a successful match to the type id register, the following should be set up: base address + 0xb8 0x00004321 40.3.6 broadcast address the broadcast address of 0xffffffffffff is recogni zed if the ?no broadcast? bit in the net- work configuration register is zero. 40.3.7 hash addressing the hash address register is 64 bits long and ta kes up two locations in the memory map. the least significant bits are stored in hash register bottom and the most significant bits in hash reg- ister top. the unicast hash enable and the multicast hash enab le bits in the network configuration register enable the reception of hash matched frames. the destination address is reduced to a 6-bit
594 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary index into the 64-bit hash register using the following hash function. the hash function is an exclusive or of every sixth bit of the destination address. hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. if the hash index points to a bit that is set in the hash register, then the frame is matched accord- ing to whether the frame is multicast or unicast. a multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register. a unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. to receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register. 40.3.8 copy all frames (or promiscuous mode) if the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. for example, frames that are too long, too short, or have fcs errors or rx_er asserted during reception are discarded and all others are received. frames with fcs errors are copied to memory if bit 19 in the network configuration register is set. 40.3.9 type id checking the contents of the type_id register are compared against the length/type id of received frames (i.e., bytes 13 and 14). bit 22 in the receive buffer descriptor status is set if there is a match. the reset state of this register is zero which is unlikely to match the length/type id of any valid ether- net frame. note: a type id match does not affect whether a frame is copied to memory. 40.3.10 vlan support an ethernet encoded 802.1q vlan tag looks like this: table 40-4. 802.1q vlan tag tpid (tag protocol identifier) 16 bits tci (tag control information) 16 bits 0x8100 first 3 bits priority, then cfi bit, last 12 bits vid
595 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the vlan tag is inserted at the 13 th byte of the frame, adding an extra four bytes to the frame. if the vid (vlan identifier) is null (0x000), this indicates a priority-tagged frame. the mac can support frame lengths up to 1536 bytes, 18 byte s more than the original ethernet maximum frame length of 1518 bytes. this is achieved by setting bit 8 in the network configuration register. the following bits in the receiv e buffer descriptor status word give information about vlan tagged frames: bit 21 set if receive frame is vlan tagged (i.e. type id of 0x8100) bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null vid). (if bit 20 is set bit 21 is set also.) bit 19, 18 and 17 set to priority if bit 21 is set bit 16 set to cfi if bit 21 is set 40.3.11 phy maintenance the register emac_man enables the emac to communicate with a phy by means of the mdio interface. it is used during auto-negotiation to ensure that the emac and the phy are config- ured for the same speed and duplex configuration. the phy maintenance register is implemented as a shift register. writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 mck cycles later when bit ten is set to zero, and bit eleven is set to one in the net- work configuration register). an interrupt is generated as this bit is set. during this time, the msb of the register is output on the mdio pin and the lsb updated from the mdio pin with each mdc cycle. this causes transmission of a phy management frame on mdio. reading during the shift operation returns the current contents of the shift register. at the end of management operation, the bits have shifted back to their original locations. for a read opera- tion, the data bits are updated with data read from the phy. it is important to write the correct values to the register to ensure a valid phy management frame is produced. the mdio interface can read ieee 802.3 clause 45 phys as well as clause 22 phys. to read clause 45 phys, bits[31:28] should be written as 0x0011. for a description of mdc generation, see the network configuration register in the ?network control register? on page 602 . 40.3.12 media independent interface the ethernet mac is capable of interfacing to both rmii and mii interfaces. the rmii bit in the emac_usrio register controls the interface that is selected. when this bit is set, the rmii inter- face is selected, else the mii interface is selected. the mii and rmii interface are capable of both 10mb/s and 100mb/s data rates as described in the ieee 802.3u standard. the signals used by the mii and rmii interfaces are described in table 40-5 . table 40-5. pin configuration pin name mii rmii etxck_erefck etxck: transmit clock erefck: reference clock ecrs ecrs: carrier sense ecol ecol: collision detect erxdv erxdv: data valid ecrsdv: carrier sense/data valid
596 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary the intent of the rmii is to provide a reduced pin count alternative to the ieee 802.3u mii. it uses 2 bits for transmit (etx0 and etx1) and tw o bits for receive (erx0 and erx1). there is a transmit enable (etxen), a receive error (er xer), a carrier sense (ecrs_dv), and a 50 mhz reference clock (etxck_erefck) for 100mb/s data rate. 40.3.12.1 rmii transmit and receive operation the same signals are used internally for both the rmii and the mii operations. the rmii maps these signals in a more pin-efficient manner. the transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. the carrier sense and data valid signals are combined into the ecrsdv signal. this signal contains information on carrier sense, fifo status, and validity of t he data. transmit error bit (etxer) and collision detect (ecol) are not used in rmii mode. erx0 - erx3 erx0 - erx3: 4-bit receiv e data erx0 - erx1: 2-bit receive data erxer erxer: receive erro r erxer: receive error erxck erxck: receive clock etxen etxen: transmit enable etxen: transmit enable etx0-etx3 etx0 - etx3: 4-bi t transmit data etx0 - etx1: 2-bit transmit data etxer etxer: transmit error table 40-5. pin configuration (continued)
597 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.4 programming interface 40.4.1 initialization 40.4.1.1 configuration initialization of the emac configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circ uits are disabled. see the description of the network control register and network configuration register earlier in this document. to change loop-back mode, the following sequence of operations must be followed: 1. write to network control register to disable transmit and receive circuits. 2. write to network control register to change loop-back mode. 3. write to network control register to re-enable transmit or receive circuits. note: these writes to network control register cannot be combined in any way. 40.4.1.2 receive buffer list receive data is written to areas of data (i.e., buffers) in system memory. these buffers are listed in another data structure that also resides in main memory. this data structure (receive buffer queue) is a sequence of descriptor entries as defined in ?receive buffer descriptor entry? on page 587 . it points to this data structure. figure 40-2. receive buffer list to create the list of buffers: 1. allocate a number ( n ) of buffers of 128 bytes in system memory. 2. allocate an area 2 n words for the receive buffer descriptor entry in system memory and create n entries in this list. mark all entries in th is list as owned by emac, i.e., bit 0 of word 0 set to 0. 3. if less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. write address of receive buffer descriptor entry to emac register receive_buffer queue pointer. receive buffer queue pointer (mac register) receive buffer 0 receive buffer 1 receive buffer n receive buffer descriptor list (in memory) (in memory)
598 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 5. the receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. 40.4.1.3 transmit buffer list transmit data is read from areas of data (the buffers) in system memory these buffers are listed in another data structure that also resides in main memory. this data structure (transmit buffer queue) is a sequence of descriptor entries (as defined in table 40-2 on page 590 ) that points to this data structure. to create this list of buffers: 1. allocate a number ( n ) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. up to 128 buffers per frame are allowed. 2. allocate an area 2 n words for the transmit buffer descriptor entry in system memory and create n entries in this list. mark all entries in this list as owned by emac, i.e. bit 31 of word 1 set to 0. 3. if fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit ? bit 30 in word 1 set to 1. 4. write address of transmit buffer descriptor entry to emac register transmit_buffer queue pointer. 5. the transmit circuits can then be enabled by writing to the network control register. 40.4.1.4 address matching the emac register-pair hash address and the four specific address register-pairs must be writ- ten with the required values. each register-pair comprises a bottom register and top register, with the bottom register being written first. the addre ss matching is disabled for a particular reg- ister-pair after the bottom-register has been written and re-enabled when the top register is written. see ?address checking block? on page 592. for details of address matching. each reg- ister-pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. 40.4.1.5 interrupts there are 14 interrupt conditions that are detected within the emac. these are ored to make a single interrupt. depending on the ov erall system design, this may be passed through a further level of interrupt collection (int errupt controller). on receipt of the interrupt signal, the cpu enters the interrupt handler (refer to the aic programmer datasheet). to ascertain which inter- rupt has been generated, read the interrupt status register. note that this register clears itself when read. at reset, all interrupts are disabled. to enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. to disable an interrupt, write to interrupt disable register with the pertinent interrupt bit set to 1. to check whether an interrupt is enabled or dis- abled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled. 40.4.1.6 transmitting frames to set up a frame for transmission: 1. enable transmit in the network control register. 2. allocate an area of system memory for transmit data. this does not have to be contigu- ous, varying byte lengths can be used as long as they conclude on byte borders. 3. set-up the transmit buffer list. 4. set the network control register to enable transmission and enable interrupts.
599 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 5. write data for transmission into these buffers. 6. write the address to transmit buffer descriptor queue pointer. 7. write control and length to word one of the transmit buffer descriptor entry. 8. write to the transmit start bit in the network control register. 40.4.1.7 receiving frames when a frame is received and the receive circuits are enabled, the emac checks the address and, in the following cases, the frame is written to system memory: if it matches one of the four specific address registers. if it matches the hash address function. if it is a broadcast address (0xf fffffffffff) and broadcasts are allowed. if the emac is configured to copy all frames. the register receive buffer queue pointer points to the next entry (see table 40-1 on page 587 ) and the emac uses this as the address in system memory to write the frame to. once the frame has been completely and successfully received an d written to system memory, the emac then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. once this is complete an interrupt re ceive complete is set. software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. if the emac is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. if there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not availabl e is set. if the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
600 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5 ethernet mac 10/100 (e mac) user interface table 40-6. ethernet mac 10/100 (emac) register mapping offset register name access reset value 0x00 network control register emac_ncr read/write 0 0x04 network configuration regi ster emac_ncfg read/write 0x800 0x08 network status register emac_nsr read-only - 0x0c reserved 0x10 reserved 0x14 transmit status register emac_tsr read/write 0x0000_0000 0x18 receive buffer queue pointer re gister emac_rbqp read/write 0x0000_0000 0x1c transmit buffer queue pointer register emac_tbqp read/write 0x0000_0000 0x20 receive status register emac_rsr read/write 0x0000_0000 0x24 interrupt status register emac_isr read/write 0x0000_0000 0x28 interrupt enable register emac_ier write-only - 0x2c interrupt disable register emac_idr write-only - 0x30 interrupt mask register emac_imr read-only 0x0000_3fff 0x34 phy maintenance register emac_man read/write 0x0000_0000 0x38 pause time register emac_ptr read/write 0x0000_0000 0x3c pause frames received register emac_pfr read/write 0x0000_0000 0x40 frames transmitted ok register emac_fto read/write 0x0000_0000 0x44 single collision frames register emac_scf read/write 0x0000_0000 0x48 multiple collision frames register emac_mcf read/write 0x0000_0000 0x4c frames received ok register emac_fro read/write 0x0000_0000 0x50 frame check sequence errors r egister emac_fcse read/write 0x0000_0000 0x54 alignment errors register emac_ale read/write 0x0000_0000 0x58 deferred transmission frames register emac_dtf read/write 0x0000_0000 0x5c late collisions register emac_lcol read/write 0x0000_0000 0x60 excessive collisions register emac_ecol read/write 0x0000_0000 0x64 transmit underrun errors register emac_tund read/write 0x0000_0000 0x68 carrier sense errors register emac_cse read/write 0x0000_0000 0x6c receive resource errors register emac_rre read/write 0x0000_0000 0x70 receive overrun errors register emac_rov read/write 0x0000_0000 0x74 receive symbol errors register emac_rse read/write 0x0000_0000 0x78 excessive length errors register emac_ele read/write 0x0000_0000 0x7c receive jabbers register emac_rja read/write 0x0000_0000 0x80 undersize frames register emac_usf read/write 0x0000_0000 0x84 sqe test errors register emac_ste read/write 0x0000_0000 0x88 received length field mismatch register emac_rle read/write 0x0000_0000
601 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 0x90 hash register bottom [31:0] register emac_hrb read/write 0x0000_0000 0x94 hash register top [63:32] register emac_hrt read/write 0x0000_0000 0x98 specific address 1 bottom re gister emac_sa1b read/write 0x0000_0000 0x9c specific address 1 top regi ster emac_sa1t read/write 0x0000_0000 0xa0 specific address 2 bottom re gister emac_sa2b read/write 0x0000_0000 0xa4 specific address 2 top register emac_sa2t read/write 0x0000_0000 0xa8 specific address 3 bottom register emac_sa3b read/write 0x0000_0000 0xac specific address 3 top register emac_sa3t read/write 0x0000_0000 0xb0 specific address 4 bottom register emac_sa4b read/write 0x0000_0000 0xb4 specific address 4 top regi ster emac_sa4t read/write 0x0000_0000 0xb8 type id checking register emac_tid read/write 0x0000_0000 0xc0 user input/output register emac_usrio read/write 0x0000_0000 0xc8-0xf8 reserved ? ? ? 0xc8 - 0xfc reserved ? ? ? table 40-6. ethernet mac 10/100 (emac) register mapping (continued) offset register name access reset value
602 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.1 network control register register name: emac_ncr access type: read/write lb: loopback asserts the loopback signal to the phy. llb: loopback local connects txd to rxd , tx_en to rx_dv , forces full duplex and drives rx_clk and tx_clk with pclk divided by 4. rx_clk and tx_clk may glitch as the emac is switched into and out of internal loop back. it is important that receive and transmit circuits have already been disabled when ma king the switch into and out of internal loop back. re: receive enable when set, enables the emac to receive data. when reset, frame reception stops immediately and the receive fifo is cleared. the receive queue pointer register is unaffected. te: transmit enable when set, enables the ethernet transmitter to send data. when reset transmission, stops immediately, the transmit fifo and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descrip- tor list. mpe: management port enable set to one to enable the management port. when zero, forces mdio to high impedance state and mdc low. clrstat: clear statistics registers this bit is write only. writing a one clears the statistics registers. incstat: increment statistics registers this bit is write only. writing a one increments all the statistics registers by one for test purposes. westat: write enable for statistics registers setting this bit to one makes the statistics regi sters writable for functional test purposes. bp: back pressure if set in half duplex mode, forces collisions on all received frames. tstart: start transmission writing one to this bit starts transmission. thalt: transmit halt writing one to this bit halts transmission as soon as any ongoing frame transmission ends. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????thalttstartbp 76543210 westat incstat clrstat mpe te re llb lb
603 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.2 network configuration register register name: emac_ncfgr access type: read/write spd: speed set to 1 to indicate 100 mbit/s operation, 0 for 10 mbit/s. the value of this pin is reflected on the speed pin. fd: full duplex if set to 1, the transmit block ignores the state of collision and carr ier sense and allows receiv e while transmitting. also co n- trols the half_duplex pin. caf: copy all frames when set to 1, all valid frames are received. jframe: jumbo frames set to one to enable jumbo frames of up to 10240 bytes to be accepted. nbc: no broadcast when set to 1, frames addressed to the broadcast address of all ones are not received. mti: multicast hash enable when set, multicast frames are received when the 6-bit hash functi on of the destination address points to a bit that is set in the hash register. uni: unicast hash enable when set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. big: receive 1536 bytes frames setting this bit means the emac receives frames up to 1536 bytes in length. normally, the emac would reject any frame above 1518 bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????irxfcsefrhddrfcsrlce 15 14 13 12 11 10 9 8 rbof pae rty clk big 76543210 uni mti nbc caf jframe ? fd spd
604 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary clk: mdc clock divider set according to system clock speed. this determines by what number system clock is divided to generate mdc. for conformance with 802.3, mdc must not exceed 2.5mhz (mdc is only active during mdio read and write operations). rty: retry test must be set to zero for normal operation. if set to one, the back off between co llisions is always one slot time. setting this bit to one helps testing the too many retries condition. also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. pae: pause enable when set, transmission pauses when a valid pause frame is received. rbof: receive buffer offset indicates the number of bytes by which the received data is offset from the start of the first receive buffer. rlce: receive length field checking enable when set, frames with measured lengths shorter than their length fields are disc arded. frames containing a type id in bytes 13 and 14 ? length/type id = 0600 ? are not be counted as length errors. drfcs: discard receive fcs when set, the fcs field of received frames are not be copied to memory. efrhd: enable frames to be received in half-duplex mode wh ile transmitting. irxfcs: ignore rx fcs when set, frames with fcs/crc errors are not rejected and no fcs error statistics are counted. for normal operation, this bit must be set to 0. clk mdc 00 mck divided by 8 (mck up to 20 mhz) 01 mck divided by 16 (mck up to 40 mhz) 10 mck divided by 32 (mck up to 80 mhz) 11 mck divided by 64 (mck up to 160 mhz) rbof offset 00 no offset from start of receive buffer 01 one-byte offset from start of receive buffer 10 two-byte offset from start of receive buffer 11 three-byte offset from start of receive buffer
605 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.3 network status register register name: emac_nsr access type: read-only mdio returns status of the mdio_in pin. use the phy main tenance register for reading managed frames rather than this bit. idle 0 = the phy management logic is idle (i.e., has completed). 1 = the phy logic is running. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????idlemdio?
606 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.4 transmit status register register name: emac_tsr access type: read/write this register, when read, provides details of the status of a tr ansmit. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ubr: used bit read set when a transmit buffer descriptor is read with its used bit set. cleared by writing a one to this bit. col: collision occurred set by the assertion of collision. cle ared by writing a one to this bit. rle: retry limit exceeded cleared by writing a one to this bit. tgo: transmit go if high transmit is active. bex: buffers exhausted mid frame if the buffers run out during transmission of a frame, then transmission stops, fcs shall be bad and tx_er asserted. cleared by writing a one to this bit. comp: transmit complete set when a frame has been transmitted. cleared by writing a one to this bit. und: transmit underrun set when transmit dma was not able to read data from memory, either because the bus was not granted in time, because a not ok hresp(bus error) was returned or because a used bit was read mi dway through frame transmission. if this occurs, the transmitter forces bad crc. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? und comp bex tgo rle col ubr
607 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.5 receive buffer queue pointer register register name: emac_rbqp access type: read/write this register points to the entry in the receive buffer queue (des criptor list) currently being used. it is written with the st art location of the receive buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origina l values after either 1024 buffers or when the wrap bit of the entry is set. reading this register returns the location of the descriptor cu rrently being accessed. this value increments as buffers are used. software should not use this register for determining where to remove received frames from the queue as it con- stantly changes as new frames are received. software should instead work its way through the buffer descriptor queue checking the used bits. receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k bo undary, in violation of section 3.6 of the amba specification. addr: receive buffer queue pointer address written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
608 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.6 transmit buffer queue pointer register register name: emac_tbqp access type: read/write this register points to the entry in the transmit buffer queue (descriptor list) currently being used. it is written with the s tart location of the transmit buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origin al values after either 1024 buffers or when the wrap bit of the entry is set. this register can only be written when bit 3 in the transmit status register is low. as transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k boundary, in violation of section 3.6 of the amba specification. addr: transmit buffer queue pointer address written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmit - ted or about to be transmitted. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
609 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.7 receive status register register name: emac_rsr access type: read/write this register, when read, provides details of the status of a re ceive. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. bna: buffer not available an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. the dma rereads the pointer each time a new frame starts un til a valid pointer is found. this bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. cleared by writing a one to this bit. rec: frame received one or more frames have been received and placed in memory. cleared by writing a one to this bit. ovr: receive overrun the dma block was unable to store the receive frame to memo ry, either because the bus was not granted in time or because a not ok hresp(bus error) was returned. the buffer is recovered if this happens. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????ovrrecbna
610 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.8 interrupt status register register name: emac_isr access type: read/write mfd: management frame done the phy maintenance register has completed its operation. cleared on read. rcomp: rece ive complete a frame has been stored in memory. cleared on read. rxubr: receive used bit read set when a receive buffer descriptor is read with its used bit set. cleared on read. txubr: transmit used bit read set when a transmit buffer descriptor is read with its used bit set. cleared on read. tund: ethernet transmit buffer underrun the transmit dma did not fetch frame data in time for it to be transmitted or hresp returned not ok. also set if a used bit is read mid-frame or when a new transmit queue pointer is written. cleared on read. rle: retry limit exceeded cleared on read. txerr: transmit error transmit buffers exhausted in mid-frame - transmit error. cleared on read. tcomp: transmit complete set when a frame has been transmitted. cleared on read. rovr: receive overrun set when the receive overrun status bit gets set. cleared on read. hresp: hresp not ok set when the dma block sees a bus error . cleared on read. pfr: pause frame received indicates a valid pause has been received. cleared on a read. ptz: pause time zero set when the pause time register, 0x38 decrements to zero. cleared on a read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
611 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.9 interrupt enable register register name: emac_ier access type: read/write mfd: management frame sent enable management done interrupt. rcomp: rece ive complete enable receive co mplete interrupt. rxubr: receive used bit read enable receive used bit read interrupt. txubr: transmit used bit read enable transmit used bit read interrupt. tund: ethernet transmit buffer underrun enable transmit underrun interrupt. rle: retry limit exceeded enable retry limit exceeded interrupt. txerr enable transmit buffers exhausted in mid-frame interrupt. tcomp: transmit complete enable transmit co mplete interrupt. rovr: receive overrun enable receive overrun interrupt. hresp: hresp not ok enable hresp not ok interrupt. pfr: pause frame received enable pause frame received interrupt. ptz: pause time zero enable pause time zero interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
612 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.10 interrupt disable register register name: emac_idr access type: read/write mfd: management frame sent disable management done interrupt. rcomp: rece ive complete disable receive comp lete interrupt. rxubr: receive used bit read disable receive used bit read interrupt. txubr: transmit used bit read disable transmit used bit read interrupt. tund: ethernet transmit buffer underrun disable transmit underrun interrupt. rle: retry limit exceeded disable retry limit exceeded interrupt. txerr disable transmit buffers exhausted in mid-frame interrupt. tcomp: transmit complete disable transmit complete interrupt. rovr: receive overrun disable receive overrun interrupt. hresp: hresp not ok disable hresp not ok interrupt. pfr: pause frame received disable pause frame received interrupt. ptz: pause time zero disable pause time zero interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
613 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.11 interrupt mask register register name: emac_imr access type: read/write mfd: management frame sent management done interrupt masked. rcomp: rece ive complete receive complete interrupt masked. rxubr: receive used bit read receive used bit read interrupt masked. txubr: transmit used bit read transmit used bit read interrupt masked. tund: ethernet transmit buffer underrun transmit underrun interrupt masked. rle: retry limit exceeded retry limit exceeded interrupt masked. txerr transmit buffers exhausted in mid-frame interrupt masked. tcomp: transmit complete transmit complete interrupt masked. rovr: receive overrun receive overrun interrupt masked. hresp: hresp not ok hresp not ok interrupt masked. pfr: pause frame received pause frame received interrupt masked. ptz: pause time zero pause time zero interrupt masked. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
614 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.12 phy maintenance register register name: emac_man access type: read/write data for a write operation this is written with the data to be written to the phy. after a read operation this contains the data read from the phy. code: must be written to 10. reads as written. rega: register address specifies the register in the phy to access. phya: phy address rw: read/write 10 is read; 01 is write. any other va lue is an invalid ph y management frame sof: start of frame must be written 01 for a valid frame. 31 30 29 28 27 26 25 24 sof rw phya 23 22 21 20 19 18 17 16 phya rega code 15 14 13 12 11 10 9 8 data 76543210 data
615 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.13 pause time register register name: emac_ptr access type: read/write ptime: pause time stores the current value of the pause time register which is decremented every 512 bit times. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ptime 76543210 ptime
616 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.14 hash register bottom register name: emac_hrb access type: read/write addr: bits 31:0 of the hash address register. see ?hash addressing? on page 593 . 40.5.15 hash register top register name: emac_hrt access type: read/write addr: bits 63:32 of the hash address register. see ?hash addressing? on page 593 . 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
617 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.16 specific address 1 bottom register register name: emac_sa1b access type: read/write addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 40.5.17 specific address 1 top register register name: emac_sa1t access type: read/write addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
618 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.18 specific address 2 bottom register register name: emac_sa2b access type: read/write addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 40.5.19 specific address 2 top register register name: emac_sa2t access type: read/write addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
619 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.20 specific address 3 bottom register register name: emac_sa3b access type: read/write addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 40.5.21 specific address 3 top register register name: emac_sa3t access type: read/write addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
620 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.22 specific address 4 bottom register register name: emac_sa4b access type: read/write addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 40.5.23 specific address 4 top register register name: emac_sa4t access type: read/write addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
621 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.24 type id checking register register name: emac_tid access type: read/write tid: type id checking for use in comparisons with rece ived frames typeid/length field. 40.5.25 user input/output register register name: emac_usrio access type: read/write rmii when set, this bit enables the rmii operation mode. when reset, it selects the mii mode. clken when set, this bit enables the transceiver input clock. setting this bit to 0 reduces power consumption when the treasurer is not used. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tid 76543210 tid 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????clkenrmii
622 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26 emac statistic registers these registers reset to zero on a read and stick at all ones when they count to their maximum value. they should be read frequently enough to prevent loss of data. the receive statis tics registers are only incremented when the receive enable bit is set in the network control register. to write to these registers, bit 7 must be set in the network control register. the sta tis- tics register block contains the following registers. 40.5.26.1 pause frames received register register name: emac_pfr access type: read/write frok: pause frames received ok a 16-bit register counting the number of good pause frames received. a good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no fcs, alignment or receive symbol errors. 40.5.26.2 frames transmitted ok register register name: emac_fto access type: read/write ftok: frames transmitted ok a 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ftok 15 14 13 12 11 10 9 8 ftok 76543210 ftok
623 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.3 single collis ion frames register register name: emac_scf access type: read/write scf: single collision frames a 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 40.5.26.4 multicollision frames register register name: emac_mcf access type: read/write mcf: multicollision frames a 16-bit register counti ng the number of frames experienc ing between two and fifteen collisio ns prior to being successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 scf 76543210 scf 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mcf 76543210 mcf
624 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.5 frames received ok register register name: emac_fro access type: read/write frok: frames received ok a 24-bit register counting the number of good frames receiv ed, i.e., address recognized and successfully copied to mem- ory. a good frame is of length 64 to 1518 bytes (1536 if bit 8 set in network configuration register) and has no fcs, alignment or receive symbol errors. 40.5.26.6 frames check sequence errors register register name: emac_fcse access type: read/write fcse: frame check sequence errors an 8-bit register counting frames that are an integral number of bytes, have bad crc and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). this register is also incremented if a symbol error is detecte d and the frame is of valid length and has an integral number of bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 frok 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 fcse
625 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.7 alignment errors register register name: emac_ale access type: read/write ale: alignment errors an 8-bit register counting frames that are not an integral number of bytes long and have bad crc when their length is trun- cated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). this register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. 40.5.26.8 deferred transmission frames register register name: emac_dtf access type: read/write dtf: deferred transmission frames a 16-bit register counting the number of frames experiencing defer ral due to carrier sense being active on their first attempt at transmission. frames invo lved in any collision are not c ounted nor are fr ames that experienced a transmit underrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ale 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dtf 76543210 dtf
626 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.9 late collisions register register name: emac_lcol access type: read/write lcol: late collisions an 8-bit register counting the number of frames that experience a collis ion after the slot time (512 bits) has expired. a late collision is counted twice; i.e., both as a collision and a late collision. 40.5.26.10 excessive collisions register register name: emac_excol access type: read/write excol: excessive collisions an 8-bit register counting the number of frames that faile d to be transmitted because t hey experienced 16 collisions. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 lcol 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 excol
627 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.11 transmit underrun errors register register name: emac_tund access type: read/write tund: transmit underruns an 8-bit register counting the number of frames not transmitte d due to a transmit dma underrun. if this register is incre- mented, then no other statistics register is incremented. 40.5.26.12 carrier sense errors register register name: emac_cse access type: read/write cse: carrier sense errors an 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after bein g asserted in a transmit frame without collis ion (no underrun). on ly incremented in half-duplex mode. the only effect of a carrier sense error is to increment this register. the behavior of the other statistics registers is unaffected by the detection of a carrier sense error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tund 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cse
628 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.13 receive reso urce errors register register name: emac_rre access type: read/write rre: receive resource errors a 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 40.5.26.14 receive overrun errors register register name: emac_rovr access type: read/write rovr: receive overrun an 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive dma overrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rre 76543210 rre 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rovr
629 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.15 receive symbol errors register register name: emac_rse access type: read/write rse: receive symbol errors an 8-bit register counting the number of frames that had rx_er asserted during reception. receive symbol errors are also counted as an fcs or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network configuration register). if the frame is larger, it is recorded as a jabber error. 40.5.26.16 excessive length errors register register name: emac_ele access type: read/write exl: excessive length errors an 8-bit register counting the number of frames received e xceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a crc error, an alignm ent error nor a rece ive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rse 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 exl
630 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.17 receive jabbers register register name: emac_rja access type: read/write rjb: receive jabbers an 8-bit register counting the number of frames received e xceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have ei ther a crc error, an alignment er ror or a receive symbol error. 40.5.26.18 undersize frames register register name: emac_usf access type: read/write usf: undersize frames an 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a crc error, an alignment error or a receive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rjb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 usf
631 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.5.26.19 sqe test errors register register name: emac_ste access type: read/write sqer: sqe test errors an 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 40.5.26.20 received length field mismatch register register name: emac_rle access type: read/write rlfm: receive length field mismatch an 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. checking is enabled through bit 16 of the netw ork configuration register. frames containing a type id in bytes 13 and 14 (i.e., length/type id 0x0600) are not counted as length field errors, neither are excessive length frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sqer 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rlfm
632 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary
633 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41. at91sam7x256/128 elec trical characteristics 41.1 absolute maximum ratings table 41-1. absolute maximum ratings* operating temperature (industrial).........-40 c to + 85 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or other con- ditions beyond those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximu m rating conditions for extended periods may affect device reliability. storage temperature............................-60c to + 150c voltage on input pins with respect to ground...........................-0.3v to + 5.5v maximum operating voltage (vddcore, and vddpll)........... ........... ........... ...1.95v maximum operating voltage (vddio, vddin and vddflash)............................3.6v total dc output current on all i/o lines 100-lead lqfp package........................................200 ma
634 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are certified for a junction temperature up to t j = 100c. note that even during startup, v vddflash must always be superior or equal to v vddcore . table 41-2. dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 1.65 1.95 v v vddpll dc supply pll 1.65 1.95 v v vddio dc supply i/os 3.0 3.6 v v vddflash dc supply flash 3.0 3.6 v v il input low-level voltage v vddio from 3.0v to 3.6v -0.3 0.8 v v ih input high-level voltage v vddio from 3.0v to 3.6v 2.0 5.5 v v ol output low-level voltage i o max, v vddio from 3.0v to 3.6v 0.4 v v oh output high-level voltage i o max, v vddio from 3.0v to 3.6v v ddio - 0.4 v i leak input leakage current pa0-pa3, pull-up resistors disabled (typ: t a = 25c, max: t a = 85c) 40 400 na other pios, pull-up resistors disabled (typ: t a = 25c, max: t a = 85c) 20 200 na i pullup input pull-up current pb27-pb30, v vddio from 3.0v to 3.6v, pax connected to ground 10 20.6 60 a other pios, v vddio from 3.0v to 3.6v, pax connected to ground 143 321 600 a i pulldown input pull-down current, (tst, erase, jtagsel) v vddio from 3.0v to 3.6v, pins connected to v vddio 135 295 550 a c in input capacitance 100 lqfp package 13.9 pf i sc static current (at91sam7x256/128) on v vddcore = 1.85v, mck = 500hz t a = 25c 12 60 a all inputs driven at 1 (including tms, tdi, tck, nrst) flash in standby mode all peripherals off t a = 85c 100 400 i o output current pa 0 - pa 3 , v vddio from 3.0v to 3.6v 16 ma pb27-pb30 and nrst, v vddio from 3.0v to 3.6v 2 ma other pios, v vddio from 3.0v to 3.6v 8 ma t slope supply core slope 6 v/ms
635 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary table 41-3. 1.8v voltage regulator characteristics symbol parameter conditions min typ max units v vddin supply voltage 3.0 3.3 3.6 v v vddout output voltage i o = 20 ma 1.81 1.85 1.89 v i vddin current consumption after startup, no load 90 a after startup, idle mode, no load 10 25 a t start startup time c load = 2.2 f, after v ddin > 2.7v 150 s i o maximum dc output current v ddin = 3.3v 100 ma i o maximum dc output current v ddin = 3.3v, in idle mode 1 ma table 41-4. brownout detector characteristics symbol parameter conditions min typ max units v bot18- vddcore threshold level 1.65 1.68 1.71 v v hyst18 vddcore hysteresis v hyst18 = v bot18+ - v bot18- 50 65 mv v bot33- vddflash threshold level 2.70 2.80 2.90 v v hyst33 vddflash hysteresis v hyst33 = v bot33+ - v bot33- 70 120 mv i dd current consumption bod on (gpnvm0 bit active) 24 30 a bod off (gpnvm0 bit inactive) 1 a t start startup time 100 200 s table 41-5. dc flash characteristics at91sam7x256/128 symbol parameter conditions min max units t pu power-up delay 45 s i sb standby current @25c onto vddcore = 1.8v onto vddflash = 3.3v 10 30 a @85c onto vddcore = 1.8v onto vddflash = 3.3v 10 120 a i cc active current random read @ 30mhz onto vddcore = 1.8v onto vddflash = 3.3v 3.0 0.8 ma write onto vddcore = 1.8v onto vddflash = 3.3v 400 5.5 a ma
636 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.3 power consumption typical power consumption of plls , slow clock and main oscillator. power consumption of power supply in two different modes: active and ultra low-power. power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 41.3.1 power consumption versus modes the values in table 41-6 and table 41-7 on page 637 are measured values of the power con- sumption with operating conditions as follows: v ddio = v ddin = v ddflash = 3.3v v ddcore = v ddpll = 1.85v t a = 25 c there is no consumption on the i/os of the device figure 41-1. measure schematics: 1.8v vddin voltage regulator vddout vddcore vddpll 3.3v vddio vddflash amp1 amp2
637 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary these figures represent the power consumpti on typically measured on the power supplies.. 41.3.2 peripheral power consumption in active mode note: 1. note: v ddcore = 1.85v, t a = 25 c table 41-6. power consumption for different modes mode conditions consumption unit active (at91sam7x256/128) voltage regulator is on. brown out detector is activated. flash is read. arm core clock is 50mhz. analog-to-digital converter activated. all peripheral clocks activated. usb transceiver enabled. onto amp1 onto amp2 50 49 ma ultra low power voltage regulator is in low-power mode. brown out detector is de-activated. flash is in standby mode. arm core in idle mode. mck @ 500hz. analog-to-digital converter de-activated. all peripheral clocks de-activated. usb transceiver disabled. ddm and ddp pins connected to ground. onto amp1 onto amp2 26 12 a table 41-7. power consumption on v ddcore (1) peripheral consumption (typ) unit pio controller 12 a/mhz usart 28 udp 20 pwm 16 twi 5 spi 16 ssc 32 timer counter channels 6 aes 123 tdes 25 can 75 arm7tdmi 160 emac 120 system peripherals (at91sam7x128/256) 200
638 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.4 crystal oscillators characteristics 41.4.1 rc oscillator characteristics 41.4.2 main oscillator characteristics note: 1. c s is the shunt capacitance 41.4.3 xin clock characteristics note: 1. these characteristics apply only wh en the main oscillator is in bypass mode (i.e., when moscen = 0 and oscbypass = 1 in the ckgr_mor register, see section 26.9.7 ?pmc clock generator main oscillator register? on page 192 . table 41-8. rc oscillator characteristics symbol parameter conditions min typ max unit 1/(t cprc ) rc oscillator frequency v ddpll = 1.65v 22 32 42 khz duty cycle 45 50 55 % t st startup time v ddpll = 1.65v 75 s i osc current consumption after startup time 1.9 a table 41-9. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 31620mhz c l1 , c l2 internal load capacitance (c l1 = c l2 ) 25 pf c l equivalent load capacitance 12.5 pf duty cycle 40 50 60 % t st startup time v ddpll = 1.2 to 2v c s = 3 pf (1) 1/(t cpmain ) = 3 mhz c s = 7 pf (1) 1/(t cpmain ) = 16 mhz c s = 7 pf (1) 1/(t cpmain ) = 20 mhz 14.5 1.4 1 ms i osc current consumption active mode 550 a standby mode 1 a table 41-10. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency (1) 50.0 mhz t cpxin xin clock period (1) 20.0 ns t chxin xin clock high half-period (1) 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period (1) 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance (1) 25 pf r in xin pull-down resistor (1) 500 k ? v xin_il v xin input low-level voltage (1) -0.3 0.2 x v ddpll v v xin_ih v xin input high-level voltage (1) 0.8 x v ddpll 1.95 v
639 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.5 pll characteristics note: startup time depends on pll rc filter. a calculation tool is provided by atmel. table 41-11. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency field out of ckgr_pll is: 00 80 160 mhz 10 150 220 mhz f in input frequency 1 32 mhz i pll current consumption active mode 4 ma standby mode 1 a
640 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.6 usb transceiver characteristics 41.6.1 electrical characteristics 41.6.2 switching characteristics table 41-12. electrical parameters symbol parameter conditions min typ max unit input levels v il low level 0.8 v v ih high level 2.0 v v di differential input sensitivity |(d+) - (d-)| 0.2 v v cm differential input common mode range 0.8 2.5 v c in transceiver capacitance capacitance to ground on each line 9.18 pf i hi-z state data line leakage 0v < v in < 3.3v -10 +10 a r ext recommended external usb series resistor in series with each usb pin with 5% 27 ? output levels v ol low level output measured with r l of 1.425 kohm tied to 3.6v 0.0 0.3 v v oh high level output measured with r l of 14.25 kohm tied to gnd 2.8 3.6 v v crs output signal crossover voltage measure conditions described in figure 41-2 1.3 2.0 v consumption i vddio current consumption transceiver enabled in input mode ddp=1 and ddm=0 105 200 a i vddcore current consumption 80 150 a table 41-13. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf 4 20 ns t fe transition fall time c load = 50 pf 4 20 ns t frfm rise/fall time matching 90 111.11 %
641 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 41-2. usb data signal rise and fall times 10% 10% 90% v crs t r t f differential data lines rise time fall time fosc = 6mhz/750khz r ext =27 ohms c load buffer (b) (a)
642 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.7 adc characteristics notes: 1. corresponds to 13 clock cycles at 5 mhz: 3 clock cycles for track and hol d acquisition time a nd 10 clock cycles for conversion. 2. corresponds to 15 clock cycles at 8 mhz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. the user can drive adc input with impedance up to: z out (shtim -470) x 10 in 8-bit resolution mode z out (shtim -589) x 7.69 in 10-bit resolution mode with shtim (sample and hold time register) expressed in ns and z out expressed in ohms. table 41-14. channel conversion time and adc clock parameter conditions min typ max units adc clock frequency 10-bit resolution mode 5 mhz adc clock frequency 8-bit resolution mode 8 mhz startup time return from idle mode 20 s track and hold acquisition time 600 ns conversion time adc clock = 5 mhz 2 s conversion time adc clock = 8 mhz 1.25 s throughput rate adc clock = 5 mhz 384 (1) ksps throughput rate adc clock = 8 mhz 533 (2) ksps table 41-15. external voltage reference input parameter conditions min typ max units advref input voltage range 2.6 v ddin v advref average current on 13 samples with adc clock = 5 mhz 200 250 a current consumption on vddin 0.55 1 ma table 41-16. analog inputs parameter min typ max units input voltage range 0v advref input leakage current 1a input capacitance 12 14 pf table 41-17. transfer characteristics parameter min typ max units resolution 10 bit integral non-linearity 3 lsb differential non-linearity 2 lsb offset error 2 lsb gain error 2 lsb
643 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.8 ac characteristics 41.8.1 master clock characteristics 41.8.2 i/o characteristics criteria used to define the maximum frequency of the i/os: output duty cycle (30%-70%) minimum output swing: 100mv to vddio - 100mv addition of rising and falling time inferior to 75% of the period notes: 1. pin group 1 = pb27 to pb30 2. pin group 2 = pa4 to pa30 and pb0 to pb30 3. pin group 3 = pa0 to pa3 4. v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf 5. v vddio from 3.0v to 3.6v, maximum external capacitor = 20pf table 41-18. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency 55 mhz table 41-19. i/o characteristics symbol parameter conditions min max units freqmax i01 pin group 1 (1) frequency load: 40 pf (4) 12.5 mhz pulseminh i01 pin group 1 (1) high level pulse width load: 40 pf (4) 40 ns pulseminl i01 pin group 1 (1) low level pulse width load: 40 pf (4) 40 ns freqmax i02 pin group 2 (2) frequency load: 40 pf (4) 25 mhz load: 20 pf (5) 51 mhz pulseminh i02 pin group 2 (2) high level pulse width load: 40 pf (4) 20 ns load: 20 pf (5) 10 ns pulseminl i02 pin group 2 (2) low level pulse width load: 40 pf (4) 20 ns load: 20 pf (5) 10 ns freqmax i03 pin group 3 (3) frequency load: 40 pf (4) 30 mhz pulseminh i03 pin group 3 (3) high level pulse width load: 40 pf (4) 16.6 ns pulseminl i03 pin group 3 (3) low level pulse width load: 40 pf (4) 16.6 ns
644 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.8.3 spi characteristics figure 41-3. spi master mode with (cpol = ncpha = 0) or (cpol= ncpha= 1) figure 41-4. spi master mode with (cpol=0 and ncpha=1) or (cpol=1 and ncpha=0) figure 41-5. spi slave mode with (cpol=0 and ncpha=1) or (cpol=1 and ncpha=0) spck miso mosi spi 2 spi 0 spi 1 spck miso mosi spi 5 spi 3 spi 4 spck miso mosi spi 6 spi 7 spi 8
645 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary figure 41-6. spi slave mode with (cpol = ncph a = 0) or (cpol= ncpha= 1) notes: 1. 3.3v domain: v vddio from 3.0v to 3.6v, maximum external capacitor = 40 pf. spck miso mosi spi 9 spi 10 spi 11 table 41-20. spi timings symbol parameter conditions min max units spi 0 miso setup time before spck rises (master) 3.3v domain (1) 28.5 ns spi 1 miso hold time after spck rises (master) 3.3v domain (1) 0ns spi 2 spck rising to mosi de lay (master) 3.3v domain (1) 2ns spi 3 miso setup time before spc k falls (master) 3.3v domain (1) 26.5 ns spi 4 miso hold time after spck falls (master) 3.3v domain (1) 0ns spi 5 spck falling to mosi delay (master) 3.3v domain (1) 2ns spi 6 spck falling to miso delay (slave) 3.3v domain (1) 28 ns spi 7 mosi setup time before spc k rises (slave) 3.3v domain (1) 2ns spi 8 mosi hold time after spc k rises (slave) 3.3v domain (1) 3ns spi 9 spck rising to miso delay (slave) 3.3v domain (1) 28 ns spi 10 mosi setup time before spc k falls (slave) 3.3v domain (1) 3ns spi 11 mosi hold time after spck falls (slave) 3.3v domain (1) 3ns
646 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.8.4 embedded flash characteristics the maximum operating frequency is given in table 41-21 but is limited by the embedded flash access time when the pro- cessor is fetching code out of it. table 41-21 gives the device maximum operating frequency depending on the field fws of the mc_fmr register. this field defines the number of wait states required to access the embedded flash memory. table 41-21. embedded flash wait states fws read operations maximum operating frequency (mhz) 0 1 cycle 30 1 2 cycles 55 2 3 cycles 55 3 4 cycles 55 table 41-22. ac flash characteristics parameter conditions min max units program cycle time per page including auto-erase 6 ms per page without auto-erase 3 ms full chip erase 15 ms
647 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.8.5 jtag/ice timings 41.8.5.1 ice interface signals note: 1. v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf figure 41-7. ice interface signals table 41-23. ice interface timing specification symbol parameter conditions min max units ice 0 tck low half-period (1) 51 ns ice 1 tck high half-period (1) 51 ns ice 2 tck period (1) 102 ns ice 3 tdi, tms, setup before tck high (1) 0ns ice 4 tdi, tms, hold after tck high (1) 3ns ice 5 tdo hold time (1) 13 ns ice 6 tck low to tdo valid (1) 20 ns tck ice 3 ice 4 ice 6 tms/tdi tdo ice 5 ice 1 ice 2 ice 0
648 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 41.8.5.2 jtag interface signals note: 1. v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf figure 41-8. jtag interface signals table 41-24. jtag interface timing specification symbol parameter conditions min max units jtag 0 tck low half-period (1) 6.5 ns jtag 1 tck high half-period (1) 5.5 ns jtag 2 tck period (1) 12 ns jtag 3 tdi, tms setup before tck high (1) 2ns jtag 4 tdi, tms hold after tck high (1) 3ns jtag 5 tdo hold time (1) 4ns jtag 6 tck low to tdo valid (1) 16 ns jtag 7 device inputs setup time (1) 0ns jtag 8 device inputs hold time (1) 3ns jtag 9 device outputs hold time (1) 6ns jtag 10 tck to device outputs valid (1) 18 ns tck jtag 9 tms/tdi tdo device outputs jtag 5 jtag 4 jtag 3 jtag 0 jtag 1 jtag 2 jtag 10 device inputs jtag 8 jtag 7 jtag 6
649 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 42. at91sam7x256/128 mech anical characteristics 42.1 thermal considerations 42.1.1 thermal data table 42-1 summarizes the thermal resistance data depending on the package. 42.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ja = package thermal resistance, junction-to-ambient (c/w), provided in table 42-1 on page 649 . jc = package thermal resistance, junction-to-case thermal resistance (c/w), provided in table 42-1 on page 649 . heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. p d = device power consumption (w) estimated from data provided in the section section 41.3 ?power consumption? on page 636 . t a = ambient temperature (c). table 42-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air lqfp100 38.3 c/w jc junction-to-case thermal resistance lqfp100 8.7 t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
650 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 42.2 package drawings figure 42-1. lqfp package drawing
651 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary this package respects the recommendations of the nemi user group. table 42-2. 100-lead lqfp package dimensions symbol millimeter inch min nom max min nom max a1.600.63 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 16.00 bsc 0.630 bsc d1 14.00 bsc 0.551 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc r2 0.08 0.20 0.003 0.008 r1 0.08 0.003 q0 3.5 7 0 3.5 7 10 0 211 12 13 11 12 13 311 12 13 11 12 13 c 0.09 0.20 0.004 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 0.008 b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc 0.020 bsc d2 12.00 0.472 e2 12.00 0.472 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 table 42-3. device and lqfp package maximum weight at91sam7x256/128 800 mg table 42-4. package reference jedec drawing reference ms-026 jesd97 classification e2 table 42-5. lqfp package characteristics moisture sensitivity level 3
652 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 42.3 soldering profile table 42-6 gives the recommended soldering profile from j-std-020c. note: the package is certified to be backward compatible with pb/sn soldering profile. a maximum of three reflow passes is allowed per component. table 42-6. soldering profile profile feature green package average ramp-up rate (217c to peak) 3 c/sec. max. preheat temperature 175c 25c 180 sec. max. temperature maintained above 217c 60 sec. to 150 sec. time within 5 c of actual peak temperature 20 sec. to 40 sec. peak temperature range 260 c ramp-down rate 6 c/sec. max. time 25 c to peak temperature 8 min. max.
653 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 43. at91sam7x256/128 or dering information table 43-1. ordering information ordering code package package type rom code revision temperature operating range at91sam7x256-au-001 lqfp 100 green 001 industrial (-40 c to 85 c) AT91SAM7X128-AU-001 lqfp 100 green 001 industrial (-40 c to 85 c)
654 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary
i 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 3 2 configuration summary of th e at91sam7x256 and at91sam7x128 3 3 at91sam7x256/128 block diagr am ................. .............. .............. .......... 4 4 signal description .............. .............. ............... .............. .............. ............ 5 5 package ............... ................ .............. ............... .............. .............. ............ 8 5.1 100-lead lqfp mechanical overview ...................................................................8 5.2 at91sam7x256/128 pinout .................................................................................8 6 power considerations ........ .............. ............... .............. .............. ............ 9 6.1 power supplies .....................................................................................................9 6.2 power consumption ..............................................................................................9 6.3 voltage regulator ..................................................................................................9 6.4 typical powering schematics .............................................................................10 7 i/o lines considerations ....... .............. .............. .............. .............. ........ 11 7.1 jtag port pins ....................................................................................................11 7.2 test pin ............................................................................................................... 11 7.3 reset pin .............................................................................................................1 1 7.4 erase pin ..........................................................................................................11 7.5 pio controller lines ............................................................................................11 7.6 i/o lines current drawing ...................................................................................12 8 processor and architecture .... ................ ................. ................ ............. 13 8.1 arm7tdmi processor ........................................................................................13 8.2 debug and test features ....................................................................................13 8.3 memory controller ...............................................................................................13 8.4 peripheral dma controller ..................................................................................14 9 memory .............. ................ ................ ............... .............. .............. .......... 15 9.1 at91sam7x256 ..................................................................................................15 9.2 at91sam7x128 ..................................................................................................15 9.3 memory mapping .................................................................................................16 9.4 embedded flash .................................................................................................17 9.5 fast flash programming interface ......................................................................19
ii 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 9.6 sam-ba boot assistant .......................................................................................19 10 system controller ........... ................ ................. .............. .............. .......... 20 10.1 system controller mapping ...............................................................................21 10.2 reset controller ................................................................................................22 10.3 clock generator ................................................................................................23 10.4 power management controller ..........................................................................24 10.5 advanced interrupt controller ...........................................................................24 10.6 debug unit ........................................................................................................25 10.7 period interval timer .........................................................................................25 10.8 watchdog timer ................................................................................................25 10.9 real-time timer .................................................................................................25 10.10 pio controllers ................................................................................................26 10.11 voltage regulator controller ...........................................................................26 11 peripherals ............ .............. .............. ............... .............. .............. .......... 27 11.1 peripheral mapping ...........................................................................................27 11.2 peripheral multiplexing on pio lines ................................................................28 11.3 pio controller a multiplexing ............................................................................29 11.4 pio controller b multiplexing ............................................................................30 11.5 peripheral identifiers .........................................................................................31 11.6 ethernet mac ....................................................................................................32 11.7 serial peripheral interface .................................................................................32 11.8 two-wire interface .............................................................................................32 11.9 usart ..............................................................................................................33 11.10 serial synchronous controller .........................................................................33 11.11 timer counter .................................................................................................33 11.12 pulse width modulation controller ..................................................................34 11.13 usb device port .............................................................................................34 11.14 can controller ................................................................................................35 11.15 128-bit advanced encryption standard ...........................................................35 11.16 triple data encryption standard .....................................................................35 11.17 analog-to-digital converter .............................................................................36 12 arm7tdmi processor overview .................... .............. .............. .......... 37 12.1 overview ...........................................................................................................37 12.2 arm7tdmi processor ......................................................................................38 13 debug and test featur es ................. ............... .............. .............. .......... 43
iii 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 13.1 description ........................................................................................................43 13.2 block diagram ...................................................................................................43 13.3 application examples ........................................................................................44 13.4 debug and test pin description ........................................................................45 13.5 functional description .......................................................................................46 14 reset controller (rstc) .... ............... ............... .............. .............. .......... 55 14.1 overview ...........................................................................................................55 14.2 block diagram ...................................................................................................55 14.3 functional description .......................................................................................56 14.4 reset controller (rstc) user interface ............................................................65 15 real-time timer (rtt) ......... .............. ............... .............. .............. .......... 69 15.1 overview ...........................................................................................................69 15.2 block diagram ...................................................................................................69 15.3 functional description .......................................................................................69 15.4 real-time timer (rtt) user interface ...............................................................71 16 periodic interval timer (pit) ................. .............. .............. ............ ........ 75 16.1 overview ...........................................................................................................75 16.2 block diagram ...................................................................................................75 16.3 functional description .......................................................................................76 16.4 periodic interval timer (pit) user interface ......................................................78 17 watchdog timer (wdt) ........... ................ ................. ................ ............. 81 17.1 overview ...........................................................................................................81 17.2 block diagram ...................................................................................................81 17.3 functional description .......................................................................................82 17.4 watchdog timer (wdt) user interface .............................................................84 18 voltage regulator mode contro ller (vreg) ............. ................. .......... 87 18.1 overview ...........................................................................................................87 18.2 voltage regulator power controller (vreg) user interface .............................88 19 memory controller (mc) .... ............... ............... .............. .............. .......... 89 19.1 overview ...........................................................................................................89 19.2 block diagram ...................................................................................................89 19.3 functional description .......................................................................................90 19.4 memory controller (mc) user interface ............................................................94 20 embedded flash controller (e fc) ............ ................ ................. .......... 99
iv 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 20.1 functional description .......................................................................................99 20.2 embedded flash controller (efc) user interface ...........................................109 21 fast flash programming inte rface (ffpi) ... .............. .............. ........... 115 21.1 overview .........................................................................................................115 21.2 parallel fast flash programming ....................................................................115 21.3 serial fast flash programming .......................................................................125 22 at91sam boot program ....... ................ ................. ................ ............. 133 22.1 description ......................................................................................................133 22.2 flow diagram ..................................................................................................133 22.3 device initialization ..........................................................................................133 22.4 sam-ba boot ..................................................................................................133 22.5 hardware and software constraints ...............................................................137 23 peripheral dma controller (pdc) ................ .............. .............. ........... 139 23.1 overview .........................................................................................................139 23.2 block diagram .................................................................................................139 23.3 functional description .....................................................................................140 23.4 peripheral dma controller (pdc) user interface ............................................142 24 advanced interrupt controller (aic) ........... .............. .............. ........... 149 24.1 overview .........................................................................................................149 24.2 block diagram .................................................................................................149 24.3 application block diagram ..............................................................................149 24.4 aic detailed block diagram ............................................................................150 24.5 i/o line description .........................................................................................150 24.6 product dependencies ....................................................................................150 24.7 functional description .....................................................................................152 24.8 advanced interrupt controller (aic) user interface .........................................162 25 clock generator ................ .............. .............. .............. .............. ........... 173 25.1 description ......................................................................................................173 25.2 slow clock rc oscillator .................................................................................173 25.3 main oscillator .................................................................................................173 25.4 divider and pll block .....................................................................................175 26 power management controller (pmc) .... ................. ................ ........... 177 26.1 description ......................................................................................................177 26.2 master clock controller ...................................................................................177
v 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 26.3 processor clock controller ..............................................................................178 26.4 usb clock controller ......................................................................................178 26.5 peripheral clock controller .............................................................................178 26.6 programmable clock output controller ...........................................................179 26.7 programming sequence ..................................................................................179 26.8 clock switching details ...................................................................................183 26.9 power management controller (pmc) user interface ....................................186 27 debug unit (dbgu) .. ................ ................ ................. ................ ........... 201 27.1 overview .........................................................................................................201 27.2 block diagram .................................................................................................202 27.3 product dependencies ....................................................................................203 27.4 uart operations ............................................................................................204 27.5 debug unit user interface ..............................................................................211 28 parallel input/output contro ller (pio) ......... .............. .............. ........... 225 28.1 overview .........................................................................................................225 28.2 block diagram .................................................................................................226 28.3 application block diagram ..............................................................................226 28.4 product dependencies ....................................................................................227 28.5 functional description .....................................................................................228 28.6 i/o lines programming example ....................................................................233 28.7 parallel input/output controller (pio) user interface ......................................234 29 serial peripheral interface (spi) ................ ................ .............. ........... 251 29.1 overview .........................................................................................................251 29.2 block diagram .................................................................................................252 29.3 application block diagram ..............................................................................252 29.4 signal description ...........................................................................................253 29.5 product dependencies ....................................................................................253 29.6 functional description .....................................................................................254 29.7 serial peripheral interface (spi) user interface .............................................263 30 two-wire interface (twi) .... .............. ............... .............. .............. ........ 277 30.1 overview .........................................................................................................277 30.2 block diagram .................................................................................................277 30.3 application block diagram ..............................................................................277 30.4 product dependencies ....................................................................................278 30.5 functional description .....................................................................................279
vi 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 30.6 two-wire interface (twi) user interface ........................................................284 31 universal synchro nous asynchronous receiver tr ansmitter (usart) 293 31.1 overview .........................................................................................................293 31.2 block diagram .................................................................................................294 31.3 application block diagram ..............................................................................295 31.4 i/o lines description ......................................................................................295 31.5 product dependencies ....................................................................................296 31.6 functional description .....................................................................................297 31.7 usart user interface ....................................................................................328 32 synchronous serial controller (ssc) .... ................. ................ ........... 347 32.1 overview .........................................................................................................347 32.2 block diagram .................................................................................................348 32.3 application block diagram ..............................................................................348 32.4 pin name list ..................................................................................................349 32.5 product dependencies ....................................................................................349 32.6 functional description .....................................................................................349 32.7 ssc application examples ..............................................................................360 32.8 synchronous serial controller (ssc) user interface ......................................362 33 timer/counter (tc) ........... .............. .............. .............. .............. ........... 385 33.1 overview .........................................................................................................385 33.2 block diagram .................................................................................................385 33.3 pin name list ..................................................................................................386 33.4 product dependencies ....................................................................................386 33.5 functional description .....................................................................................387 33.6 timer/counter (tc) user interface ..................................................................400 34 pulse width modulation c ontroller (pwm) . .............. .............. ........... 419 34.1 overview .........................................................................................................419 34.2 block diagram .................................................................................................419 34.3 i/o lines description .......................................................................................420 34.4 product dependencies ....................................................................................420 34.5 functional description .....................................................................................421 34.6 pulse width modulation controller (pwm) user interface ..............................429 35 usb device port (udp) ....... .............. ............... .............. .............. ........ 439 35.1 description ......................................................................................................439
vii 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 35.2 block diagram .................................................................................................440 35.3 product dependencies ....................................................................................440 35.4 typical connection ..........................................................................................442 35.5 functional description .....................................................................................443 35.6 usb device port (udp) user interface ...........................................................457 36 analog-to-digital converter (adc) .............. .............. .............. ........... 475 36.1 overview .........................................................................................................475 36.2 block diagram .................................................................................................475 36.3 signal description ...........................................................................................476 36.4 product dependencies ....................................................................................476 36.5 functional description .....................................................................................477 36.6 analog-to-digital converter (adc) user interface ...........................................481 37 advanced encryption standard (aes) ............. .............. ............ ........ 491 37.1 overview .........................................................................................................491 37.2 product dependencies ....................................................................................491 37.3 functional description .....................................................................................492 37.4 advanced encrypti on standard (aes) us er interface .......... ................ ...........498 38 triple data encryption s ystem (tdes) ....... .............. .............. ........... 509 38.1 description ......................................................................................................509 38.2 product dependencies ....................................................................................509 38.3 functional description .....................................................................................510 38.4 triple des (tdes) user interface ...................................................................516 39 controller area network (c an) ............ ................. ................ ............. 529 39.1 description ......................................................................................................529 39.2 block diagram .................................................................................................530 39.3 application block diagram ..............................................................................531 39.4 i/o lines description ......................................................................................531 39.5 product dependencies ....................................................................................531 39.6 can controller features .................................................................................532 39.7 functional description .....................................................................................544 39.8 controller area network (can) user interface ...............................................557 40 ethernet mac 10/100 (emac) .. ............... ................. ................ ........... 585 40.1 overview .........................................................................................................585 40.2 block diagram .................................................................................................585
viii 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary 40.3 functional description .....................................................................................586 40.4 programming interface ....................................................................................597 40.5 ethernet mac 10/100 (emac) user interface .................................................600 41 at91sam7x256/128 electric al characteristics ...... ................ ........... 633 41.1 absolute maximum ratings .............................................................................633 41.2 dc characteristics ..........................................................................................634 41.3 power consumption ........................................................................................636 41.4 crystal oscillators characteristics ...................................................................638 41.5 pll characteristics .........................................................................................639 41.6 usb transceiver characteristics .....................................................................640 41.7 adc characteristics .......................................................................................642 41.8 ac characteristics ...........................................................................................643 42 mechanical characteristics ..... ................ ................. ................ ........... 649 42.1 thermal considerations ..................................................................................649 42.2 package drawings ..........................................................................................650 42.3 soldering profile ..............................................................................................652 43 at91sam7x256/128 ordering information ............... .............. ........... 653 table of contents....... ................ ................. ................ ................. ............. i revision history.......... ................ ................. ................ ................. ........... ix
ix 6120a?atarm?01-sep-05 at91sam7x256/128 preliminary revision history doc. rev. date comments change request ref. 6120a 01-sep-05 first issue.
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